ST STM32G471 User Manual

RM0440 Rev 4 527/2126
RM0440 Flexible static memory controller (FSMC)
571
Mode A - SRAM/FRAM/PSRAM (CRAM) OE toggling
Figure 56. Mode A read access waveforms
1. NBL[1:0] are driven low during the read access
3:2 MTYP As needed, exclude 0x2 (NOR Flash memory)
1 MUXE 0x0
0 MBKEN 0x1
Table 130. FMC_BTRx bitfields (mode 1)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD HCLK cycles for read
accesses, DATAHLD+1 HCLK cycles for write accesses).
29:28 ACCMOD Don’t care
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 0.
Table 129. FMC_BCRx bitfields (mode 1) (continued)
Bit number Bit name Value to set
MSv41681V1
A[25:0]
Memory transaction
NBL[x:0]
NEx
NOE
Data driven by memory
NWE
Data bus
NBLSET
HCLK
cycles
ADDSET HCLK cycles DATAST HCLK cycles DATAHLD
HCLK cycles
High

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English