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General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440

1240/2126 RM0440 Rev 4

Figure 366. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR

preloaded)

Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a

counter underflow event.

An Update event can be generate at each counter underflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller)

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1

preload registers. Then no update event occurs until UDIS bit has been written to 0.

However, the counter restarts from the current auto-reload value, whereas the counter of the

prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when

clearing the counter on the capture event.

MSv62304V1

tim_psc_ck

tim_cnt_ck

Counter register

Update event (UEV)

Counter overflow

Update interrupt flag

(UIF)

03 04 05

07F1

F3 F4

F5F0

CEN

Auto-reload preload

Write a new value in TIMx_ARR

Auto-reload shadow

ST STM32G471 User Manual

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