High-resolution timer (HRTIM) RM0440
856/2126 RM0440 Rev 4
Note: A compare value greater than the period register value does not generate a compare match
event.
Counter operating mode
Timer A..F operate in continuous (free-running) mode or in single-shot manner where
counting is started by a reset event, using the CONT bit in the HRTIM_TIMxCR control
register. An additional RETRIG bit allows you to select whether the single-shot operation is
retriggerable or non-retriggerable. Details of operation are summarized on Table 215 and on
Figure 185 and Figure 186.
The TxEN bit can be cleared at any time to disable the timer and stop the counting.
Table 214. Period and compare registers min and max values
CKPSC[2:0] value Min
(1)
1. The value 0x0000 can be written in CMP1 and CMP3 registers only, to skip a PWM pulse. See Section :
Null duty cycle exception case for details.
Max
0 0x0060 0xFFDF
1 0x0030 0xFFEF
2 0x0018 0xFFF7
3 0x000C 0xFFFB
4 0x0006 0xFFFD
≥ 5 0x0003 0xFFFD
Table 215. Timer operating modes
CONT RETRIG Operating mode
Start / stop conditions
Clocking and event generation
00
Single-shot
Non-retriggerable
Setting the TxEN bit enables the timer but does not start the counter.
A first reset event starts the counting and any subsequent reset is ignored
until the counter reaches the PER value.
The PER event is then generated and the counter is stopped.
A reset event re-starts the counting operation from 0x0000.
01
Single-shot
Retriggerable
Setting the TxEN bit enables the timer but does not start the counter.
A reset event starts the counting if the counter is stopped, otherwise it
clears the counter. When the counter reaches the PER value, the PER
event is generated and the counter is stopped.
A reset event re-starts the counting operation from 0x0000.
1 X Continuous mode
Setting the TxEN bit enables the timer and starts the counter
simultaneously.
When the counter reaches the PER value, it rolls-over to 0x0000 and
resumes counting.
The counter can be reset at any time.
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