Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1090/2126 RM0440 Rev 4
Table 255 lists the internal sources connected to the tim_ocref_clr input multiplexer.
Table 253. Timer break2 interconnect
tim_brk2 inputs TIM1 TIM8 TIM20
TIM_BKIN2 TIM1_BKIN2 pin TIM8_BKIN2 pin TIM20_BKIN2 pin
tim_brk2_cmp1 comp1_out comp1_out comp1_out
tim_brk2_cmp2 comp2_out comp2_out comp2_out
tim_brk2_cmp3 comp3_out comp3_out comp3_out
tim_brk2_cmp4 comp4_out comp4_out comp4_out
tim_brk2_cmp5 comp5_out comp5_out comp5_out
tim_brk2_cmp6 comp6_out comp6_out comp6_out
tim_brk2_cmp7 comp7_out comp7_out comp7_out
tim_brk2_cmp8 Reserved
Table 254. System break interconnect
tim_sys_brk
inputs
TIM1 / TIM8 / TIM20
Enable bit in SYSCFG_CFGR2
register
tim_sys_brk0 Cortex
®
-M4 with FPU LOCKUP CLL
tim_sys_brk1 Programmable Voltage Detector (PVD) PVDL
tim_sys_brk2 SRAM parity error SPL
tim_sys_brk3 Flash ECC error ECCL
tim_sys_brk4 Clock Security System (CSS) None (always enabled)
Table 255. Interconnect to the ocref_clr input multiplexer
Timer OCREF clear
signal
Timer OCREF clear signals assignment
TIM1 TIM8 TIM20
tim_ocref_clr0 comp1_out comp1_out comp1_out
tim_ocref_clr1 comp2_out comp2_out comp2_out
tim_ocref_clr2 comp3_out comp3_out comp3_out
tim_ocref_clr3 comp4_out comp4_out comp4_out
tim_ocref_clr4 comp5_out comp5_out comp5_out
tim_ocref_clr5 comp6_out comp6_out comp6_out
tim_ocref_clr6 comp7_out comp7_out comp7_out
tim_ocref_clr7 Reserved
To Next Page
Loading...
Need help?
General
