Flexible static memory controller (FSMC) RM0440
560/2126 RM0440 Rev 4
19.7.2 NAND Flash supported memories and transactions
Table 152 shows the supported devices, access modes and transactions. Transactions not
allowed (or not supported) by the NAND Flash controller are shown in gray.
19.7.3 Timing diagrams for NAND Flash memory
The NAND Flash memory bank is managed through a set of registers:
• Control register: FMC_PCR
• Interrupt status register: FMC_SR
• ECC register: FMC_ECCR
• Timing register for Common memory space: FMC_PMEM
• Timing register for Attribute memory space: FMC_PATT
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any NAND Flash access, plus one parameter that
defines the timing for starting driving the data bus when a write access is performed.
Figure 72 shows the timing parameter definitions for common memory accesses, knowing
that Attribute memory space access timings are similar.
Table 152. Supported memories and transactions
Device Mode R/W
AHB
data size
Memory
data size
Allowed/
not allowed
Comments
NAND 8-bit
Asynchronous R 8 8 Y -
Asynchronous W 8 8 Y -
Asynchronous R 16 8 Y Split into 2 FMC accesses
Asynchronous W 16 8 Y Split into 2 FMC accesses
Asynchronous R 32 8 Y Split into 4 FMC accesses
Asynchronous W 32 8 Y Split into 4 FMC accesses
NAND 16-bit
Asynchronous R 8 16 Y -
Asynchronous W 8 16 N -
Asynchronous R 16 16 Y -
Asynchronous W 16 16 Y -
Asynchronous R 32 16 Y Split into 2 FMC accesses
Asynchronous W 32 16 Y Split into 2 FMC accesses
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