ST STM32G471

RM0440 Rev 4 529/2126
RM0440 Flexible static memory controller (FSMC)
571
3:2 MTYP As needed, exclude 0x2 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1
Table 132. FMC_BTRx bitfields (mode A)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD HCLK cycles for read
accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for read
accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
Minimum value for ADDSET is 0.
Table 133. FMC_BWTRx bitfields (mode A)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for write
accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
Minimum value for ADDSET is 0.
Table 131. FMC_BCRx bitfields (mode A) (continued)
Bit number Bit name Value to set