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General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440

1236/2126 RM0440 Rev 4

Figure 360. Counter timing diagram with prescaler division change from 1 to 4

29.4.4 Counter modes

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An Update event can be generated at each counter overflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.

This is to avoid updating the shadow registers while writing new values in the preload

registers. Then no update event occurs until the UDIS bit has been written to 0. However,

the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate

does not change). In addition, if the URS bit (update request selection) in TIMx_CR1

flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and

capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC

• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock

frequencies when TIMx_ARR=0x36.

MSv50999V1

1230123

tim_psc_ck

CEN

Counter register

Update event (UEV)

Prescaler control register

Write a new value in TIMx_PSC

Prescaler buffer

Prescaler counter

F7 F8 F9

tim_cnt_ck

ST STM32G471 User Manual

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