Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1162/2126 RM0440 Rev 4
The error assertion is delayed to the transition 0 to 1 when in up-counting. This is cope with
narrow index pulses in gated A and B mode, as shown on Figure 349 below.
Figure 349. Up-counting encoder error detection
MSv62357V1
tim_ti1
tim_ti2
IERRF
Index
tim_ti1
tim_ti2
IERRF
Index
Counter
5 6 7 0 1
3
2
Counter 5 6 7 0 1
3
2
Error detected Error asserted
Error detected Abort (index detection)
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