RM0440 Rev 4 79/2126
RM0440 System and memory overview
79
2.1.3 S-bus
This bus connects the system bus of the Cortex
®
-M4 with FPU core to the BusMatrix. This
bus is used by the core to access data located in a peripheral or SRAM area. The targets of
this bus are the internal SRAM, the AHB1 peripherals including the APB1 and APB2
peripherals, the AHB2 peripherals and the external memories through the QUADSPI or the
FSMC.
The CCM SRAM is also accessible on this bus to allow continuous mapping with SRAM1
and SRAM2.
2.1.4 DMA-bus
This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this
bus are the SRAM1, SRAM2 and CCM SRAM, the AHB1 peripherals including the APB1
and APB2 peripherals, the AHB2 peripherals and the external memories through the
QUADSPI or the FSMC.
2.1.5 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of up to five masters (CPU AHB,
system bus, DCode bus, ICode bus, DMA1, DMA2, ) and up to nine slaves (FLASH,
SRAM1, SRAM2, CCM SRAM, AHB1 (including APB1 and APB2), AHB2, QUADSPI, and
FSMC).
AHB/APB bridges
The two AHB/APB bridges provide full synchronous connections between the AHB and the
two APB buses, allowing flexible selection of the peripheral frequency.
Refer to Section 2.2.2: Memory map and register boundary addresses on page 81 for the
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and
Flash memory interface). Before using a peripheral you have to enable its clock in the
RCC_AHBxENR and the RCC_APBxENR registers.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
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