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RM0440 Rev 4
191
1/21
26
RM0440
Inter-integ
rated
circuit (I2C) interface
1928
41.6
I2C interrupts
The table below gives the lis
t of I2C interrup
t requests.
T
able 389. I2C In
terrupt requests
Interrupt
acronym
Interrupt
event
Event
flag
Enable
control bit
Interrupt clear
method
Exit the
Sleep
mode
Exit the
Stop
mode
Exit the
Standby
modes
I2C
I2C_EV
Receive
buffer
not empty
RXNE
RXIE
Read
I2C_RXDR
register
Ye
s
No
No
T
ransmit buffer
interrupt status
TXIS
TXIE
Write
I2C_TXDR
register
Stop detection
interrupt flag
STOPF
ST
OPIE
Wri
t
e
STOPCF=1
T
ransfer
Complete
Reload
TCR
TCIE
Write I2C_CR2
with
NBYTES[7:0] ≠
0
T
ransfer
complete
TC
Write ST
ART=1
or STOP=1
Address
matched
ADDR
ADDRIE
Wri
t
e
ADDRCF=1
Ye
s
(1)
NACK
reception
NACKF
NACKIE
Wri
t
e
NACKCF=1
No
I2C_ER
Bus error
BERR
ERRIE
Wri
t
e
BERRCF=1
Ye
s
No
No
Arbitration loss
ARLO
Wri
t
e
ARLOCF=1
Overrun/Under
run
OVR
Write OVRCF=1
PEC error
PECERR
Wri
t
e
PECERRCF=1
T
imeout/t
LOW
error
TIMEOUT
Wri
t
e
TIMEOUTCF=1
SMBus
Alert
ALERT
Wri
t
e
ALERTCF=1
1.
The
ADDR match even
t can wake up the device from Stop mode on
ly if the I2C instance supports the Wakeup from Stop
mode feature. Refer to
Section
41.3: I2C implementation
.
1910
1912
Table of Contents
Table of Contents
2
List of Tables
49
Documentation Conventions
72
General Information
72
List of Abbreviations for Registers
72
Glossary
73
Product Category Definition
73
Availability of Peripherals
73
Table 1. STM32G4 Series Memory Density
73
Table 2. Product Specific Features
74
System and Memory Overview
77
System Architecture
77
D-Bus
78
Figure 1. System Architecture
78
I-Bus
78
Busmatrix
79
DMA-Bus
79
S-Bus
79
Memory Organization
80
Introduction
80
Figure 2. Memory Map
81
Memory Map and Register Boundary Addresses
81
Addresses
82
Bit Banding
85
Table 3. STM32G4 Series Memory Map and Peripheral Register Boundary
85
Embedded SRAM
86
CCM SRAM Write Protection
87
Parity Check
87
Table 4. CCM SRAM Organization
87
CCM SRAM Erase
88
CCM SRAM Read Protection
88
Flash Memory Overview
89
Boot Configuration
89
Table 5. Boot Modes
89
Table 6. Memory Mapping Versus Boot Mode/Physical Remap
91
Embedded Flash Memory (FLASH) for Category 3 Devices
92
Introduction
92
FLASH Main Features
92
FLASH Functional Description
93
Flash Memory Organization
93
Table 7. Flash Module - 512/256/128 KB Dual Bank Organization (64 Bits Read Width)
94
Error Code Correction (ECC)
95
Table 8. Flash Module - 512/256/128 KB Single Bank Organization (128 Bits Read Width)
95
Read Access Latency
96
Table 9. Number of Wait States According to CPU Clock (HCLK) Frequency
97
Adaptive Real-Time Memory Accelerator (ART Accelerator)
98
Figure 3. Sequential 16-Bit Instructions Execution (64-Bit Read Data Width)
99
Flash Program and Erase Operations
100
Flash Main Memory Erase Sequences
101
Flash Main Memory Programming Sequences
102
(Dbank=1)
106
Read-While-Write (RWW) Available Only in Dual Bank Mode
106
FLASH Option Bytes
108
Option Bytes Description
108
Table 10. Option Byte Format
108
Table 11. Option Byte Organization
108
Option Bytes Programming
116
FLASH Memory Protection
119
Read Protection (RDP)
119
Table 12. Flash Memory Read Protection Status
119
Figure 4. Changing the Read Protection (RDP) Level
121
Table 13. Access Status Versus Protection Level and Execution Modes
121
Proprietary Code Readout Protection (PCROP)
122
Table 14. PCROP Protection
123
Write Protection (WRP)
124
Disabling Core Debug Access
125
Securable Memory Area
125
Table 15. WRP Protection
125
Forcing Boot from Flash Memory
126
FLASH Interrupts
126
Table 16. Flash Interrupt Request
126
Figure 5. Example of Disabling Core Debug Access
126
FLASH Registers
127
Flash Access Control Register (FLASH_ACR)
127
Flash Power-Down Key Register (FLASH_PDKEYR)
128
Flash Key Register (FLASH_KEYR)
129
Flash Option Key Register (FLASH_OPTKEYR)
129
Flash Status Register (FLASH_SR)
130
Flash Control Register (FLASH_CR)
132
Flash ECC Register (FLASH_ECCR)
134
Flash Option Register (FLASH_OPTR)
136
Flash PCROP1 Start Address Register (FLASH_PCROP1SR)
138
Flash PCROP1 End Address Register (FLASH_PCROP1ER)
139
Flash Bank 1 WRP Area a Address Register (FLASH_WRP1AR)
140
Flash Bank 1 WRP Area B Address Register (FLASH_WRP1BR)
140
Flash PCROP2 End Address Register (FLASH_PCROP2ER)
141
Flash PCROP2 Start Address Register (FLASH_PCROP2SR)
141
Flash Bank 2 WRP Area a Address Register (FLASH_WRP2AR)
142
Flash Bank 2 WRP Area B Address Register (FLASH_WRP2BR)
143
Flash Securable Area Bank1 Register (FLASH_SEC1R)
143
Flash Securable Area Bank2 Register (FLASH_SEC2R)
144
FLASH Register Map
145
Table 17. Flash Interface - Register Map and Reset Values
145
Embedded Flash Memory (FLASH)
147
For Category 4 Devices
147
Introduction
147
FLASH Main Features
147
FLASH Functional Description
148
Flash Memory Organization
148
Table 18. Flash Module Organization (64 Bits Read Width)
148
Error Code Correction (ECC)
149
Read Access Latency
149
Table 19. Number of Wait States According to CPU Clock (HCLK) Frequency
149
Adaptive Real-Time Memory Accelerator (ART Accelerator)
150
Figure 6. Sequential 16-Bit Instructions Execution (64-Bit Read Data Width)
152
Flash Program and Erase Operations
153
Flash Main Memory Erase Sequences
154
Flash Main Memory Programming Sequences
155
FLASH Option Bytes
159
Option Bytes Description
159
Table 20. Option Byte Format
159
Table 21. Option Byte Organization
159
Option Bytes Programming
164
FLASH Memory Protection
165
Read Protection (RDP)
165
Table 22. Flash Memory Read Protection Status
165
Figure 7. Changing the Read Protection (RDP) Level
167
Table 23. Access Status Versus Protection Level and Execution Modes
167
Proprietary Code Readout Protection (PCROP)
168
Table 24. PCROP Protection
169
Write Protection (WRP)
169
Securable Memory Area
170
Table 25. WRP Protection
170
Disabling Core Debug Access
171
Figure 8. Example of Disabling Core Debug Access
171
Forcing Boot from Flash Memory
171
FLASH Interrupts
172
Table 26. Flash Interrupt Request
172
FLASH Registers
173
Flash Access Control Register (FLASH_ACR)
173
Flash Power-Down Key Register (FLASH_PDKEYR)
174
Flash Key Register (FLASH_KEYR)
175
Flash Option Key Register (FLASH_OPTKEYR)
175
Flash Status Register (FLASH_SR)
176
Flash Control Register (FLASH_CR)
177
Flash ECC Register (FLASH_ECCR)
179
Flash Option Register (FLASH_OPTR)
180
Flash PCROP1 Start Address Register (FLASH_PCROP1SR)
182
Flash PCROP1 End Address Register (FLASH_PCROP1ER)
183
Flash WRP Area a Address Register (FLASH_WRP1AR)
183
Flash Securable Area Register (FLASH_SEC1R)
184
Flash WRP Area B Address Register (FLASH_WRP1BR)
184
FLASH Register Map
186
Table 27. Flash Interface - Register Map and Reset Values
186
Embedded Flash Memory (FLASH) for Category 2 Devices
188
Introduction
188
FLASH Main Features
188
FLASH Functional Description
189
Flash Memory Organization
189
Table 28. Flash Module Organization (64 Bits Read Width)
189
Error Code Correction (ECC)
190
Read Access Latency
190
Table 29. Number of Wait States According to CPU Clock (HCLK) Frequency
190
Adaptive Real-Time Memory Accelerator (ART Accelerator)
191
Figure 9. Sequential 16-Bit Instructions Execution (64-Bit Read Data Width)
193
Flash Program and Erase Operations
194
Flash Main Memory Erase Sequences
195
Flash Main Memory Programming Sequences
196
FLASH Option Bytes
200
Option Bytes Description
200
Table 30. Option Byte Format
200
Table 31. Option Byte Organization
200
Option Bytes Programming
205
FLASH Memory Protection
206
Read Protection (RDP)
206
Table 32. Flash Memory Read Protection Status
206
Figure 10. Changing the Read Protection (RDP) Level
208
Table 33. Access Status Versus Protection Level and Execution Modes
208
Proprietary Code Readout Protection (PCROP)
209
Table 34. PCROP Protection
210
Write Protection (WRP)
210
Securable Memory Area
211
Table 35. WRP Protection
211
Disabling Core Debug Access
212
Figure 11. Example of Disabling Core Debug Access
212
Forcing Boot from Flash Memory
212
FLASH Interrupts
213
Table 36. Flash Interrupt Request
213
FLASH Registers
214
Flash Access Control Register (FLASH_ACR)
214
Flash Power-Down Key Register (FLASH_PDKEYR)
215
Flash Key Register (FLASH_KEYR)
216
Flash Option Key Register (FLASH_OPTKEYR)
216
Flash Status Register (FLASH_SR)
217
Flash Control Register (FLASH_CR)
218
Table 37. Flash Interface - Register Map and Reset Values
227
Figure 12. STM32G4 Series Power Supply Overview
230
Table 38. Range 1 Boost Mode Configuration
233
Figure 13. Brown-Out Reset Waveform
236
Figure 14. PVD Thresholds
237
Table 39. PVM Features
237
Figure 15. Low-Power Modes Possible Transitions
239
Table 40. Low-Power Mode Summary
240
Table 41. Functionalities Depending on the Working Mode
241
Table 42. Low-Power Run
244
Table 43. Sleep
246
Table 44. Low-Power Sleep
247
Table 45. Stop 0 Mode
249
Table 46. Stop 1 Mode
250
Table 47. Standby Mode
252
Table 48. Shutdown Mode
254
Power Status Register 1 (PWR_SR1)
259
Power Status Register 2 (PWR_SR2)
260
Power Status Clear Register (PWR_SCR)
261
Power Port a Pull-Down Control Register (PWR_PDCRA)
262
Power Port a Pull-Up Control Register (PWR_PUCRA)
262
Power Port B Pull-Down Control Register (PWR_PDCRB)
263
Power Port B Pull-Up Control Register (PWR_PUCRB)
263
Power Port C Pull-Down Control Register (PWR_PDCRC)
264
Power Port C Pull-Up Control Register (PWR_PUCRC)
264
Power Port D Pull-Down Control Register (PWR_PDCRD)
265
Power Port D Pull-Up Control Register (PWR_PUCRD)
265
Power Port E Pull-Down Control Register (PWR_PDCRE)
266
Power Port E Pull-Up Control Register (PWR_PUCRE)
266
Power Port F Pull-Down Control Register (PWR_PDCRF)
267
Power Port F Pull-Up Control Register (PWR_PUCRF)
267
Power Port G Pull-Down Control Register (PWR_PDCRG)
268
Power Port G Pull-Up Control Register (PWR_PUCRG)
268
Power Control Register (PWR_CR5)
269
PWR Register Map and Reset Value Table
270
Table 49. PWR Register Map and Reset Values
270
Power Reset
272
Reset
272
Reset and Clock Control (RCC)
272
System Reset
272
Figure 16. Simplified Diagram of the Reset Circuit
273
Clocks
274
RTC Domain Reset
274
Figure 17. Clock Tree
277
Figure 18. HSE/ LSE Clock Sources
278
HSE Clock
278
HSI16 Clock
279
HSI48 Clock
280
LSE Clock
280
Pll
280
LSI Clock
281
System Clock (SYSCLK) Selection
281
Clock Security System (CSS)
282
Clock Security System on LSE
282
Clock Source Frequency Versus Voltage Scaling
282
Table 50. Clock Source Frequency
282
ADC Clock
283
Figure 19. Frequency Measurement with TIM15 in Capture Mode
285
Figure 20. Frequency Measurement with TIM16 in Capture Mode
285
Figure 21. Frequency Measurement with TIM17 in Capture Mode
286
Figure 22. Frequency Measurement with TIM5 in Capture Mode
286
Table 51. RCC Register Map and Reset Values
334
Table 52. CRS Features
339
Figure 23. CRS Block Diagram
340
Figure 24. CRS Counter Behavior
341
Table 53. Effect of Low-Power Modes on CRS
343
Table 54. Interrupt Control Bits
343
Table 55. CRS Register Map and Reset Values
349
Figure 25. Basic Structure of an I/O Port Bit
351
Figure 26. Basic Structure of a 5-Volt Tolerant I/O Port Bit
351
Table 56. Port Bit Configuration Table
352
Figure 27. Input Floating/Pull Up/Pull down Configurations
356
Figure 28. Output Configuration
357
Figure 29. Alternate Function Configuration
357
Figure 30. High Impedance-Analog Configuration
358
Table 57. GPIO Register Map and Reset Values
367
Table 58. BOOSTEN and ANASWVDD Set/Reset
372
Table 59. SYSCFG Register Map and Reset Values
380
Table 60. STM32G4 Series Peripherals Interconnect Matrix
382
Table 61. Interconnect 1
384
Table 62. Interconnect 12
385
Table 63. Interconnect 13
385
Table 64. Interconnect 14
385
Table 67. Interconnect 17
390
Table 68. Interconnect 15
391
Table 73. Interconnect 2
395
Table 74. Interconnect 3
396
Table 75. Interconnect 4
397
Table 76. Interconnect 5
398
Table 77. Interconnect 6
398
Table 78. Interconnect 7
398
Table 79. Interconnect 8
399
Table 80. Interconnect 9
399
Table 81. Interconnect 10
400
Table 82. Interconnect 11
400
Table 83. Interconnect 18
401
Table 84. Interconnect 16
401
Table 85. DMA1 and DMA2 Implementation
403
Figure 31. DMA Block Diagram
404
Table 86. DMA Internal Input/Output Signals
405
Table 87. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)
411
Table 88. DMA Interrupt Requests
413
Table 89. DMA Register Map and Reset Values
421
Table 90. DMAMUX Instantiation
425
Table 91. DMAMUX: Assignment of Multiplexer Inputs to Resources
426
Table 92. DMAMUX: Assignment of Trigger Inputs to Resources
427
Table 93. DMAMUX: Assignment of Synchronization Inputs to Resources
428
Figure 32. DMAMUX Block Diagram
429
Table 94. DMAMUX Signals
430
Figure 33. Synchronization Mode of the DMAMUX Request Line Multiplexer Channel
432
Figure 34. Event Generation of the DMA Request Line Multiplexer Channel
432
Table 95. DMAMUX Interrupts
434
Table 96. DMAMUX Register Map and Reset Values
439
Table 97. STM32G4 Series Vector Table
442
Figure 35. Configurable Interrupt/Event Block Diagram
447
Figure 36. External Interrupt/Event GPIO Mapping
449
Table 98. EXTI Lines Connections
449
Table 99. Extended Interrupt/Event Controller Register Map and Reset Values
460
Figure 37. CRC Calculation Unit Block Diagram
462
Table 100. CRC Internal Input/Output Signals
462
Table 101. CRC Register Map and Reset Values
466
Table 102. CORDIC Functions
468
Table 103. Cosine Parameters
468
Table 104. Sine Parameters
469
Table 105. Phase Parameters
469
Table 106. Modulus Parameters
470
Table 107. Arctangent Parameters
471
Table 108. Hyperbolic Cosine Parameters
471
Table 109. Hyperbolic Sine Parameters
472
Table 110. Hyperbolic Arctangent Parameters
472
Table 111. Natural Logarithm Parameters
473
Table 112. Natural Log Scaling Factors and Corresponding Ranges
473
Table 113. Square Root Parameters
474
Table 114. Square Root Scaling Factors and Corresponding Ranges
474
Figure 38. CORDIC Convergence for Trigonometric Functions
475
Figure 39. CORDIC Convergence for Hyperbolic Functions
476
Figure 40. CORDIC Convergence for Square Root
477
Table 115. Precision Vs. Number of Iterations
477
Table 116. CORDIC Register Map and Reset Value
485
Figure 41. Block Diagram
487
Figure 42. Input Buffer Areas
489
Figure 43. Circular Input Buffer
490
Figure 44. Circular Input Buffer Operation
491
Figure 45. Circular Output Buffer
492
Figure 46. Circular Output Buffer Operation
493
Figure 47. FIR Filter Structure
495
Figure 48. IIR Filter Structure (Direct Form 1)
497
Table 117. Valid Combinations for Read and Write Methods
499
Figure 49. X1 Buffer Initialization
502
Figure 50. Filtering Example 1
503
Figure 51. Filtering Example 2
504
Table 118.FMAC Register Map and Reset Values
513
Figure 52. FMC Block Diagram
515
Figure 53. FMC Memory Banks
518
Table 119. NOR/PSRAM Bank Selection
518
Table 120. NOR/PSRAM External Memory Address
518
Table 121. NAND Memory Mapping and Timing Registers
519
Table 122. NAND Bank Selection
519
Table 123. Programmable NOR/PSRAM Access Parameters
521
Table 124. Non-Multiplexed I/O nor Flash Memory
521
Table 125. 16-Bit Multiplexed I/O nor Flash Memory
522
Table 126. Non-Multiplexed I/Os PSRAM/SRAM
522
Table 127. 16-Bit Multiplexed I/O PSRAM
522
And Transactions
523
Table 128. nor Flash/Psram: Example of Supported Memories
523
Figure 54. Mode 1 Read Access Waveforms
525
Figure 55. Mode 1 Write Access Waveforms
526
Table 129. Fmc_Bcrx Bitfields (Mode 1)
526
Figure 56. Mode a Read Access Waveforms
527
Table 130. Fmc_Btrx Bitfields (Mode 1)
527
Figure 57. Mode a Write Access Waveforms
528
Table 131. Fmc_Bcrx Bitfields (Mode A)
528
Table 132. Fmc_Btrx Bitfields (Mode A)
529
Table 133. Fmc_Bwtrx Bitfields (Mode A)
529
Figure 58. Mode 2 and Mode B Read Access Waveforms
530
Figure 59. Mode 2 Write Access Waveforms
530
Figure 60. Mode B Write Access Waveforms
531
Table 134. Fmc_Bcrx Bitfields (Mode 2/B)
531
Table 135. Fmc_Btrx Bitfields (Mode 2/B)
532
Table 136. Fmc_Bwtrx Bitfields (Mode 2/B)
532
Figure 61. Mode C Read Access Waveforms
533
Figure 62. Mode C Write Access Waveforms
533
Table 137. Fmc_Bcrx Bitfields (Mode C)
534
Table 138. Fmc_Btrx Bitfields (Mode C)
534
Figure 63. Mode D Read Access Waveforms
535
Table 139. Fmc_Bwtrx Bitfields (Mode C)
535
Figure 64. Mode D Write Access Waveforms
536
Table 140. Fmc_Bcrx Bitfields (Mode D)
536
Table 141. Fmc_Btrx Bitfields (Mode D)
537
Table 142. Fmc_Bwtrx Bitfields (Mode D)
537
Figure 65. Muxed Read Access Waveforms
538
Figure 66. Muxed Write Access Waveforms
539
Table 143. Fmc_Bcrx Bitfields (Muxed Mode)
539
Table 144. Fmc_Btrx Bitfields (Muxed Mode)
540
Figure 67. Asynchronous Wait During a Read Access Waveforms
541
Figure 68. Asynchronous Wait During a Write Access Waveforms
542
Figure 69. Wait Configuration Waveforms
544
Figure 70. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
545
Table 146. Fmc_Btrx Bitfields (Synchronous Multiplexed Read Mode)
546
Figure 71. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
547
Table 148. Fmc_Btrx Bitfields (Synchronous Multiplexed Write Mode)
548
Table 149. Programmable NAND Flash Access Parameters
557
Table 150. 8-Bit NAND Flash
558
Table 151. 16-Bit NAND Flash
559
Table 152. Supported Memories and Transactions
560
Figure 72. NAND Flash Controller Waveforms for Common Memory Access
561
Figure 73. Access to Non 'CE Don't Care' NAND-Flash
562
Table 153. ECC Result Relevant Bits
569
Table 154. FMC Register Map and Reset Values
570
Figure 74. QUADSPI Block Diagram When Dual-Flash Mode Is Disabled
572
Figure 75. QUADSPI Block Diagram When Dual-Flash Mode Is Enabled
573
Table 155. QUADSPI Pins
573
Figure 76. an Example of a Read Command in Quad Mode
574
Figure 77. an Example of a DDR Command in Quad Mode
577
Figure 78. Ncs When CKMODE = 0 (T = CLK Period)
585
Figure 79. Ncs When CKMODE = 1 in SDR Mode (T = CLK Period)
585
Figure 80. Ncs When CKMODE = 1 in DDR Mode (T = CLK Period)
586
Figure 81. Ncs When CKMODE = 1 with an Abort (T = CLK Period)
586
Table 156. QUADSPI Interrupt Requests
587
Table 157. QUADSPI Register Map and Reset Values
600
Table 158. Main ADC Features
603
Figure 82. ADC Block Diagram
604
Table 159. ADC Internal Input/Output Signals
605
Table 160. ADC Input/Output Pins
605
Figure 84. ADC1 Connectivity
608
Figure 85. ADC2 Connectivity
609
Figure 86. ADC3 Connectivity
610
Figure 87. ADC4 Connectivity
611
Figure 88. ADC5 Connectivity
612
Figure 89. ADC Calibration
615
Figure 90. Updating the ADC Calibration Factor
616
Figure 91. Mixing Single-Ended and Differential Channels
617
Figure 92. Enabling / Disabling the ADC
618
Figure 93. Bulb Mode Timing Diagram
621
Figure 94. Analog to Digital Conversion Time
624
Figure 95. Stopping Ongoing Regular Conversions
625
Figure 96. Stopping Ongoing Regular and Injected Conversions
625
Table 161. Configuring the Trigger Polarity for Regular External Triggers
626
Table 162. Configuring the Trigger Polarity for Injected External Triggers
626
Figure 97. Triggers Sharing between ADC Master and ADC Slave
627
Table 163. ADC1/2 - External Triggers for Regular Channels
627
Table 164. ADC1/2 - External Trigger for Injected Channels
628
Table 165. ADC3/4/5 - External Triggers for Regular Channels
629
Table 166. ADC3/4/5 - External Triggers for Injected Channels
630
Figure 98. Injected Conversion Latency
633
Figure 100. Example of JSQR Queue of Context (Trigger Change)
636
Figure 99. Example of JSQR Queue of Context (Sequence Change)
636
Figure 101. Example of JSQR Queue of Context with Overflow before Conversion
637
Figure 102. Example of JSQR Queue of Context with Overflow During Conversion
637
Figure 103. Example of JSQR Queue of Context with Empty Queue (Case JQM=0)
638
Figure 104. Example of JSQR Queue of Context with Empty Queue (Case JQM=1)
639
Figure 105. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs During an Ongoing Conversion
639
Figure 106. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs During an Ongoing Conversion and a New
640
Figure 107. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs Outside an Ongoing Conversion
640
Trigger Occurs
640
Figure 108. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=1)
641
Figure 109. Flushing JSQR Queue of Context by Setting ADDIS=1 (JQM=0)
641
Figure 110. Flushing JSQR Queue of Context by Setting ADDIS=1 (JQM=1)
642
Table 167. TSAR Timings Depending on Resolution
643
Figure 111. Single Conversions of a Sequence, Software Trigger
644
Figure 112. Continuous Conversion of a Sequence, Software Trigger
644
Figure 113. Single Conversions of a Sequence, Hardware Trigger
645
Figure 114. Continuous Conversions of a Sequence, Hardware Trigger
645
Table 168. Offset Computation Versus Data Resolution
646
Figure 115. Right Alignment (Offset Disabled, Unsigned Value)
647
Figure 116. Right Alignment (Offset Enabled, Signed Value)
648
Figure 117. Left Alignment (Offset Disabled, Unsigned Value)
648
Figure 118. Left Alignment (Offset Enabled, Signed Value)
649
Figure 119. Example of Overrun (OVR)
650
Figure 120. AUTODLY=1, Regular Conversion in Continuous Mode, Software Trigger
653
(Discen=0; Jdiscen=0)
654
Figure 121. AUTODLY=1, Regular HW Conversions Interrupted by Injected Conversions
654
(Discen=1, Jdiscen=1)
655
Figure 123. AUTODLY=1, Regular Continuous Conversions Interrupted by Injected Conversions
656
Figure 124. AUTODLY=1 in Auto- Injected Mode (JAUTO=1)
656
Figure 125. Analog Watchdog Guarded Area
657
Table 169. Analog Watchdog Channel Selection
657
Table 170. Analog Watchdog 1 Comparison
658
Figure 126. Adcy_Awdx_Out Signal Generation (on All Regular Channels)
659
Table 171. Analog Watchdog 2 and 3 Comparison
659
Figure 127. Adcy_Awdx_Out Signal Generation (Awdx Flag Not Cleared by Software)
660
Figure 128. Adcy_Awdx_Out Signal Generation (on a Single Regular Channel)
660
Figure 129. Adcy_Awdx_Out Signal Generation (on All Injected Channels)
660
Figure 130. 20-Bit to 16-Bit Result Truncation
662
Figure 131. Numerical Example with 5-Bit Shift and Rounding
662
Table 172. Maximum Output Results Versus N and M (Gray Cells Indicate Truncation)
662
Figure 132. Triggered Regular Oversampling Mode (TROVS Bit = 1)
664
Figure 133. Regular Oversampling Modes (4X Ratio)
665
Figure 134. Regular and Injected Oversampling Modes Used Simultaneously
665
Figure 135. Triggered Regular Oversampling with Injection
666
Figure 136. Oversampling in Auto-Injected Mode
666
Table 173. Oversampler Operating Modes Summary
667
Figure 137. Dual ADC Block Diagram (1)
669
Figure 138. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
670
Figure 139. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
672
Figure 140. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
673
Figure 141. Interleaved Mode on 1 Channel in Single Conversion Mode: Dual ADC Mode
674
Figure 142. Interleaved Conversion with Injection
674
Figure 143. Alternate Trigger: Injected Group of each ADC
675
Figure 144. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
676
Figure 145. Alternate + Regular Simultaneous
677
Figure 146. Case of Trigger Occurring During Injected Conversion
677
Case 1: Master Interrupted First
678
Case 2: Slave Interrupted First
678
Figure 147. Interleaved Single Channel CH0 with Injected Sequence CH11, CH12
678
Figure 148. Two Interleaved Channels (CH1, CH2) with Injected Sequence CH11, CH12
678
Figure 149. Two Interleaved Channels (CH1, CH2) with Injected Sequence CH11, CH12
678
Figure 150. DMA Requests in Regular Simultaneous Mode When Mdma=0B00
679
Figure 151. DMA Requests in Regular Simultaneous Mode When Mdma=0B10
680
Figure 152. DMA Requests in Interleaved Mode When Mdma=0B10
680
Figure 153. Temperature Sensor Channel Block Diagram
682
Figure 154. VBAT Channel Block Diagram
683
Figure 155. VREFINT Channel Block Diagram
684
Table 174. ADC Interrupts Per each ADC
685
Table 175. DELAY Bits Versus ADC Resolution
720
Table 176. ADC Global Register Map
721
For Master ADC, 0X100 for Slave ADC)
722
Table 177. ADC Register Map and Reset Values for each ADC
722
Common Registers) Offset = 0X300
724
Table 179. DAC Implementation
726
Figure 156. Dual-Channel DAC Block Diagram
727
Table 180. DAC Input/Output Pins
728
Table 181. DAC Input/Output Signals
728
Table 182. DAC1 Interconnection
729
Table 183. DAC2 Interconnection
730
Table 184. DAC3 Interconnection
731
Table 185. DAC4 Interconnection
732
Figure 157. Data Registers in Single DAC Channel Mode
734
Figure 158. Data Registers in Dual DAC Channel Mode
735
Table 186. Data Format (Case of 12-Bit Data)
735
Table 187. HFSEL Description
736
Figure 159. Timing Diagram for Conversion with Trigger Disabled TEN = 0
737
Figure 160. DAC LFSR Register Calculation Algorithm
739
Figure 161. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
739
Figure 162. DAC Triangle Wave Generation
740
Figure 163. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
740
Figure 164. DAC Sawtooth Wave Generation (Stdirx=0)
741
Figure 165. DAC Sawtooth Wave Generation (Stdirx=1)
741
Figure 166. DAC Sawtooth STINCTRIG and STRSTTRIG Priority (STDIR = 0)
742
Table 188. Sample and Refresh Timings
743
Figure 167. DAC Sample and Hold Mode Phase Diagram
744
Table 189. Channel Output Modes Summary
745
Table 190. Effect of Low-Power Modes on DAC
752
Table 191. DAC Interrupts
752
Table 192. DAC Register Map and Reset Values
772
Table 193. VREF Buffer Modes
774
Table 194. VREFBUF Register Map and Reset Values
777
Table 195. Compx Non-Inverting Input Assignment
779
Table 196. Compx Inverting Input Assignment
779
Figure 169. Comparator Hysteresis
780
Figure 170. Comparator Output Blanking
781
Table 197. Blanking Sources
781
Table 198. Comparator Behavior in Low-Power Modes
781
Table 199. COMP Register Map and Reset Values
784
Table 200. Operational Amplifier Possible Connection
787
Figure 171. Standalone Mode: External Gain Setting Mode
789
Figure 172. Follower Configuration
790
Figure 173. PGA Mode, Internal Gain Setting (X2/X4/X8/X16/X32/X64)
791
Inverting Input Not Used
791
Figure 174. PGA Mode, Internal Gain Setting (X2/X4/X8/X16/X32/X64)
792
Inverting Input Used for Filtering
792
Figure 175. PGA Mode, Non-Inverting Gain Setting (X2/X4/X8/X16/X32/X64)
793
Or Inverting Gain Setting (X-1/X-3/X-7/X-15/X-31/X-63)
793
Figure 176. PGA Mode, Non-Inverting Gain Setting (X2/X4/X8/X16/X32/X64) or Inverting Gain Setting (X-1/X-3/X-7/X-15/X-31/X-63) with Filtering
794
Figure 177. Example Configuration
794
Table 201. Operating Modes and Calibration
795
Figure 178. Timer Controlled Multiplexer Mode
797
Table 202. Effect of Low-Power Modes on the OPAMP
797
Table 203. OPAMP Register Map and Reset Values
828
Figure 179. RNG Block Diagram
831
Table 204. RNG Internal Input/Output Signals
831
Figure 180. Entropy Source Model
832
Figure 181. RNG Initialization Overview
835
Table 205. RNG Interrupt Requests
838
Table 206. RNG Register Map and Reset Map
843
Figure 182. High-Resolution Timer Overview
847
Table 207. HRTIM Inputs/Outputs Summary
848
Table 208. External Events Mapping and Associated Features
850
Table 209. Update Enable Inputs and Sources
850
Table 210. Burst Mode Clock Sources from General Purpose Timer
850
Table 211. Fault Inputs
851
Table 212. HRTIM DAC Triggers Connections
851
HRTIM = 170 Mhz
852
Figure 183. Counter and Capture Register Format Vs Clock Prescaling Factor
853
Figure 184. Timer a
855
Table 214. Period and Compare Registers Min and Max Values
856
Table 215. Timer Operating Modes
856
Figure 185. Continuous Timer Operation
857
Figure 186. Single-Shot Timer Operation
857
Figure 187. Timer Reset Resynchronization (Prescaling Ratio above 32)
859
Figure 188. Repetition Rate Versus Hrtim_Repxr Content in Continuous Mode
860
Figure 189. Repetition Counter Behavior in Single-Shot Mode
860
Figure 190. Compare Events Action on Outputs: Set on Compare 1, Reset on Compare 2
862
Table 216. Events Mapping Across Timer a to F
862
Table 217. Interleaved Mode Selection
863
Table 218. Compare 1..3 Values in Interleaved Mode
864
Figure 191. Timer a Timing Unit Capture Circuitry
866
Figure 192. Auto-Delayed Overview (Compare 2 Only)
867
Figure 193. Auto-Delayed Compare
868
Figure 194. Triggered-Half Mode Example
870
Figure 195. Push-Pull Mode Block Diagram
871
Figure 196. Push-Pull Mode Example
872
Figure 197. Push-Pull with Deadtime
873
Figure 198. Complementary Outputs with Deadtime Insertion
874
Figure 199. Deadtime Insertion Versus Deadtime Sign (1 Indicates Negative Deadtime)
874
Figure 200. Complementary Outputs for Low Pulsewidth (Sdtrx = Sdtfx = 0)
875
Figure 201. Complementary Outputs for Low Pulsewidth (Sdtrx = Sdtfx = 1)
875
Table 219. Deadtime Resolution and Max Absolute Values
875
Figure 202. Complementary Outputs for Low Pulsewidth (Sdtrx = 0, Sdtfx = 1)
876
Figure 203. Complementary Outputs for Low Pulsewidth (Sdtrx = 1, Sdtfx=0)
876
Figure 204. Master Timer Overview
877
Figure 205. Basic Symmetric Waveform in Up-Down Counting Mode
878
Figure 206. Complex Symmetric Waveform in Up-Down Counting Mode
879
Figure 207. Asymmetric Waveform in Up-Down Counting Mode
879
Figure 208. External Event Management in Up-Down Counting Mode
880
Figure 209. Interleaved Up-Down Counter Operation
880
Figure 210. Interleaved Up-Down Counter Operation
881
Figure 211. Push-Pull Up-Down Mode Example
881
Figure 212. Up-Down Mode with "Greater Than" Comparison
882
Table 220. Roll-Over Event Destination and Mode Programming
882
Figure 213. Up-Down Mode with Output Set on Period Event, for OUTROM[1:0]=10
883
Figure 214. Repetition Counter Behavior in Up-Down Counting Mode
884
Table 221. Eexfltr[3:0] Codes Depending on UDM Bit Setting
884
Figure 215. Short Distance Set/Reset Management for Narrow Pulse Generation
886
Figure 216. External Event Conditioning Overview (1 Channel Represented)
889
Table 222. External Events Features
890
Table 223. Output Set/Reset Latency and Jitter Versus External Event Operating Mode
891
Figure 217. Latency to External Events Falling Edge (Counter Reset and Output Set)
892
Figure 218. Latency to External Events (Output Reset on External Event)
892
Figure 219. Event Blanking Mode
893
Figure 220. Event Postpone Mode
893
Table 224. Filtering Signals Mapping Per Timer
894
Figure 221. External Trigger Blanking with Edge-Sensitive Trigger
895
Figure 222. External Trigger Blanking, Level Sensitive Triggering
895
Figure 223. Event Windowing Mode
896
Table 225. Windowing Signals Mapping Per Timer (EEFLTR[3:0] = 1111)
896
Figure 224. External Trigger Windowing with Edge-Sensitive Trigger
897
Figure 225. External Trigger Windowing, Level Sensitive Triggering
897
Figure 226. External Event Counter - Channel a
898
Figure 227. External Event Counter Cumulative Mode (Eevxrstm = 1, Eevxcnt = 2)
899
Figure 228. Delayed Idle Mode Entry
900
Figure 229. Burst Mode and Delayed Protection Priorities (DIDL = 0)
901
Figure 230. Burst Mode and Delayed Protection Priorities (DIDL = 1)
902
Figure 231. Balanced Idle Protection Example
903
Table 226. HRTIM Preloadable Control Registers and Associated Update Sources
906
Figure 232. Resynchronized Timer Update (TAU=1 in HRTIM_TIMBCR)
908
Figure 233. Early Turn-ON and Early Turn-OFF Behavior in "Greater Than" PWM Mode
910
Table 227. Master Timer Update Event Propagation
911
Table 228. Timx Update Event Propagation
911
Table 229. Reset Events Able to Generate an Update
913
Table 230. Update Event Propagation for a Timer Reset
913
Figure 234. Output Management Overview
915
Table 231. Output State Programming, X= A..F, y = 1 or 2
915
Figure 235. HRTIM Output States and Transitions
916
Figure 236. Burst Mode Operation Example
917
Table 232. Timer Output Programming for Burst Mode
918
Figure 237. Burst Mode Trigger on External Event
920
Figure 238. Delayed Burst Mode Entry with Deadtime Enabled and Idlesx = 1
921
Figure 239. Delayed Burst Mode Entry During Deadtime
922
Figure 240. Burst Mode Exit When the Deadtime Generator Is Enabled
923
Figure 241. Burst Mode Emulation Example
925
Figure 242. Carrier Frequency Signal Insertion
925
Figure 243. HRTIM Outputs with Chopper Mode Enabled
926
Figure 244. Fault Protection Circuitry (FAULT1 Fully Represented, FAULT2
927
Table 233. Fault Inputs
927
Figure 245. Fault Signal Filtering (Fltxf[3:0]= 0010: F SAMPLING = Fhrtim, N = 4)
928
Table 234. Sampling Rate and Filter Length Vs Fltfxf[3:0] and Clock Setting
929
Table 235. Fault Input Blanking Events
929
Figure 246. Fault Counter Cumulative Mode (Fltxrstm = 1, Fltxcnt[3:0] = 2)
930
Table 236. Fault 1..6 Counter Reset Source
930
Figure 247. Auxiliary Outputs
932
Figure 248. Auxiliary and Main Outputs During Burst Mode (Didlx = 0)
933
Figure 249. Deadtime Distortion on Auxiliary Output When Exiting Burst Mode
933
Table 237. Effect of Sync Event Versus Timer Operating Modes
935
Figure 250. Counter Behavior in Synchronized Start Mode
937
Figure 251. ADC Trigger Selection Overview
938
Figure 252. ADC Triggers
939
Figure 253. ADC Trigger Post-Scaling in Up-Counting Mode
940
Figure 254. ADC Trigger Post-Scaling in Up/Down Counting Mode
940
Figure 255. Combining Several Updates on a Single Hrtim_Dac_Trgx Output
941
Table 238. DAC Dual Channel Trigger Example
943
Figure 256. DAC Triggers for Slope Compensation
944
Figure 257. DAC Triggers Overview
945
Table 239. HRTIM Interrupt Summary
946
Table 240. HRTIM DMA Request Summary
948
Figure 258. DMA Burst Overview
949
Figure 259. Burst DMA Operation Flowchart
950
Figure 260. Registers Update Following DMA Burst Transfer
951
Figure 261. Buck Converter Topology
953
Figure 262. Dual Buck Converter Management
954
Figure 263. Synchronous Rectification Depending on Output Current
954
Figure 264. Buck with Synchronous Rectification
955
Figure 265. 3-Phase Interleaved Buck Converter
955
Figure 266. 3-Phase Interleaved Buck Converter Control
956
Figure 267. Transition Mode PFC
957
Figure 268. Transition Mode PFC Waveforms
958
Table 241. HRTIM Register Map and Reset Values - Master Timer
1074
Table 243. HRTIM Register Map and Reset Values - Common Functions
1080
Figure 269. Advanced-Control Timer Block Diagram
1085
Table 244. TIM Input/Output Pins
1086
Table 245. TIM Internal Input/Output Signals
1086
Table 246. Interconnect to the Tim_Ti1 Input Multiplexer
1087
Table 247. Interconnect to the Tim_Ti2 Input Multiplexer
1088
Table 248. Interconnect to the Tim_Ti3 Input Multiplexer
1088
Table 249. Interconnect to the Tim_Ti4 Input Multiplexer
1088
Table 250. Timx Internal Trigger Connection
1088
Table 251. Interconnect to the Tim_Etr Input Multiplexer
1089
Table 252. Timer Break Interconnect
1089
Table 253. Timer Break2 Interconnect
1090
Table 254. System Break Interconnect
1090
Table 255. Interconnect to the Ocref_Clr Input Multiplexer
1090
Figure 270. Counter Timing Diagram with Prescaler Division Change from 1 to 2
1092
Figure 271. Counter Timing Diagram with Prescaler Division Change from 1 to 4
1092
Figure 272. Counter Timing Diagram, Internal Clock Divided by 1
1094
Figure 273. Counter Timing Diagram, Internal Clock Divided by 2
1094
Figure 274. Counter Timing Diagram, Internal Clock Divided by 4
1095
Figure 275. Counter Timing Diagram, Internal Clock Divided by N
1095
(Timx_Arr Not Preloaded)
1096
Figure 276. Counter Timing Diagram, Update Event When ARPE=0
1096
(Timx_Arr Preloaded)
1097
Figure 277. Counter Timing Diagram, Update Event When ARPE=1
1097
Figure 278. Counter Timing Diagram, Internal Clock Divided by 1
1098
Figure 279. Counter Timing Diagram, Internal Clock Divided by 2
1099
Figure 280. Counter Timing Diagram, Internal Clock Divided by 4
1099
Figure 281. Counter Timing Diagram, Internal Clock Divided by N
1100
Figure 282. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
1100
Figure 283. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
1102
Figure 284. Counter Timing Diagram, Internal Clock Divided by 2
1102
Figure 285. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
1103
Figure 286. Counter Timing Diagram, Internal Clock Divided by N
1103
Figure 287. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
1104
Figure 288. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
1105
Figure 289. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
1106
Figure 290. External Trigger Input Block
1107
Figure 291. Control Circuit in Normal Mode, Internal Clock Divided by 1
1108
Figure 292. Tim_Ti2 External Clock Connection Example
1108
Figure 293. Control Circuit in External Clock Mode 1
1109
Figure 294. External Trigger Input Block
1110
Figure 295. Control Circuit in External Clock Mode 2
1111
Figure 296. Capture/Compare Channel (Example: Channel 1 Input Stage)
1111
Figure 297. Capture/Compare Channel 1 Main Circuit
1112
Figure 298. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch. 2, 3 and 4)
1112
Figure 299. Output Stage of Capture/Compare Channel (Channel 5, Idem Ch. 6)
1113
Figure 300. PWM Input Mode Timing
1115
Figure 301. Output Compare Mode, Toggle on Tim_Oc1
1117
Figure 302. Edge-Aligned PWM Waveforms (ARR=8)
1118
Figure 303. Center-Aligned PWM Waveforms (ARR=8)
1119
Figure 304. Dithering Principle
1120
Figure 305. Data Format and Register Coding in Dithering Mode
1121
Figure 306. PWM Resolution Vs Frequency
1122
Figure 307. PWM Dithering Pattern
1123
Table 256. CCR and ARR Register Change Dithering Pattern
1123
Figure 308. Dithering Effect on Duty Cycle in Center-Aligned PWM Mode
1124
Table 257. CCR Register Change Dithering Pattern in Center-Aligned PWM Mode
1124
Figure 309. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
1126
Figure 310. Combined PWM Mode on Channel 1 and 3
1127
Figure 311. 3-Phase Combined PWM Signals with Multiple Trigger Pulses Per Period
1128
Figure 312. Complementary Output with Symmetrical Dead-Time Insertion
1129
Figure 313. Asymmetrical Deadtime
1130
Figure 314. Dead-Time Waveforms with Delay Greater than the Negative Pulse
1130
Figure 315. Dead-Time Waveforms with Delay Greater than the Positive Pulse
1130
Figure 316. Break and Break2 Circuitry Overview
1133
Figure 317. Various Output Behavior in Response to a Break Event on Tim_Brk (OSSI = 1)
1135
Figure 318. PWM Output State Following Tim_Brk and Tim_Brk2 Assertion (OSSI=1)
1136
Table 258. Behavior of Timer Outputs Versus Tim_Brk/Tim_Brk2 Inputs
1136
Figure 319. PWM Output State Following Tim_Brk Assertion (OSSI=0)
1137
Figure 320. Output Redirection (Tim_Brk2 Request Not Represented)
1138
Table 259. Break Protection Disarming Conditions
1138
Figure 321. Tim_Ocref_Clr Input Selection Multiplexer
1139
Figure 322. Clearing Timx Tim_Ocxref
1140
Figure 323. 6-Step Generation, COM Example (OSSR=1)
1141
Figure 324. Example of One Pulse Mode
1142
Figure 325. Retriggerable One Pulse Mode
1143
Figure 326. Pulse Generator Circuitry
1144
Figure 327. Pulse Generation on Compare Event, for Edge-Aligned and Encoder Modes
1145
Figure 328. Extended Pulsewidth in Case of Concurrent Triggers
1146
Table 260. Counting Direction Versus Encoder Signals (CC1P = CC2P = 0)
1147
Figure 329. Example of Counter Operation in Encoder Interface Mode
1148
Figure 330. Example of Encoder Interface Mode with Tim_Ti1Fp1 Polarity Inverted
1148
Figure 331. Quadrature Encoder Counting Modes
1149
Figure 332. Direction Plus Clock Encoder Mode
1150
Figure 333. Directional Clock Encoder Mode (CC1P = CC2P = 0)
1150
Figure 334. Directional Clock Encoder Mode (CC1P = CC2P = 1)
1151
Table 261. Counting Direction Versus Encoder Signals and Polarity Settings
1151
Figure 335. Index Gating Options
1152
Figure 336. Jittered Index Signals
1152
Figure 337. Index Generation for IPOS[1:0] = 11
1153
Figure 338. Counter Reading with Index Gated on Channel a (IPOS[1:0] = 11)
1154
Figure 339. Counter Reading with Index Ungated (IPOS[1:0] = 00)
1154
Figure 340. Counter Reading with Index Gated on Channel a and B
1155
Figure 341. Encoder Mode Behavior in Case of Narrow Index Pulse (IPOS[1:0] = 11)
1156
Figure 342. Counter Reset Narrow Index Pulse (Closer View, ARR = 0X07)
1157
Figure 343. Index Behavior in X1 and X2 Mode (IPOS[1:0] = 01)
1158
Figure 344. Directional Index Sensitivity
1159
Figure 345. Counter Reset as Function of FIDX Bit Setting
1159
Figure 346. Index Behavior in Clock + Direction Mode, IPOS[0] = 1
1160
Figure 347. Index Behavior in Directional Clock Mode, IPOS[0] = 1
1160
Figure 348. State Diagram for Quadrature Encoded Signals
1161
Figure 349. Up-Counting Encoder Error Detection
1162
Figure 350. Down-Counting Encode Error Detection
1163
Figure 351. Encoder Mode Change with Preload Transferred on Update (SMSPS = 0)
1164
Figure 352. Measuring Time Interval between Edges on 3 Signals
1165
Figure 353. Example of Hall Sensor Interface
1167
Figure 354. Control Circuit in Reset Mode
1168
Figure 355. Control Circuit in Gated Mode
1169
Figure 356. Control Circuit in Trigger Mode
1170
Figure 357. Control Circuit in External Clock Mode 2 + Trigger Mode
1171
Table 262. DMA Request
1173
Table 263. Effect of Low-Power Modes on TIM1/TIM8/TIM20
1174
Table 264. Interrupt Requests
1174
Table 265. Output Control Bits for Complementary Tim_Ocx and Tim_Ocxn Channels
1201
With Break Feature
1201
Table 266. Timx Register Map and Reset Values
1224
Table 267. STM32G4 Series General Purpose Timers
1228
Figure 358. General-Purpose Timer Block Diagram
1229
Table 268. TIM Input/Output Pins
1230
Table 269. TIM Internal Input/Output Signals
1230
Table 270. Interconnect to the Tim_Ti1 Input Multiplexer
1231
Table 271. Interconnect to the Tim_Ti2 Input Multiplexer
1232
Table 272. Interconnect to the Tim_Ti3 Input Multiplexer
1232
Table 273. Interconnect to the Tim_Ti4 Input Multiplexer
1232
Table 274. Timx Internal Trigger Connection
1232
Table 275. Interconnect to the Tim_Etr Input Multiplexer
1233
Table 276. Interconnect to the Tim_Ocref_Clr Input Multiplexer
1234
Figure 359. Counter Timing Diagram with Prescaler Division Change from 1 to 2
1235
Figure 360. Counter Timing Diagram with Prescaler Division Change from 1 to 4
1236
Figure 361. Counter Timing Diagram, Internal Clock Divided by 1
1237
Figure 362. Counter Timing Diagram, Internal Clock Divided by 2
1237
Figure 363. Counter Timing Diagram, Internal Clock Divided by 4
1238
Figure 364. Counter Timing Diagram, Internal Clock Divided by N
1238
Figure 365. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
1239
Figure 366. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
1240
Figure 367. Counter Timing Diagram, Internal Clock Divided by 1
1241
Figure 368. Counter Timing Diagram, Internal Clock Divided by 2
1242
Figure 369. Counter Timing Diagram, Internal Clock Divided by 4
1242
Figure 370. Counter Timing Diagram, Internal Clock Divided by N
1243
Figure 371. Counter Timing Diagram, Update Event
1243
Figure 372. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
1245
Figure 373. Counter Timing Diagram, Internal Clock Divided by 2
1245
Figure 374. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
1246
Figure 375. Counter Timing Diagram, Internal Clock Divided by N
1246
Figure 376. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
1247
Figure 377. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
1248
Figure 378. Control Circuit in Normal Mode, Internal Clock Divided by 1
1249
Figure 379. Tim_Ti2 External Clock Connection Example
1249
Figure 380. Control Circuit in External Clock Mode 1
1250
Figure 381. External Trigger Input Block
1251
Figure 382. Control Circuit in External Clock Mode 2
1252
Figure 383. Capture/Compare Channel (Example: Channel 1 Input Stage)
1252
Figure 384. Capture/Compare Channel 1 Main Circuit
1253
Figure 385. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch.2, 3 and 4)
1253
Figure 386. PWM Input Mode Timing
1256
Figure 387. Output Compare Mode, Toggle on Tim_Oc1
1258
Figure 388. Edge-Aligned PWM Waveforms (ARR=8)
1259
Figure 389. Center-Aligned PWM Waveforms (ARR=8)
1260
Figure 390. Dithering Principle
1261
Figure 391. Data Format and Register Coding in Dithering Mode
1262
Figure 392. PWM Resolution Vs Frequency (16-Bit Mode)
1263
Figure 393. PWM Resolution Vs Frequency (32-Bit Mode)
1263
Figure 394. PWM Dithering Pattern
1264
Figure 395. Dithering Effect on Duty Cycle in Center-Aligned PWM Mode
1265
Table 277. CCR and ARR Register Change Dithering Pattern
1265
Table 278. CCR Register Change Dithering Pattern in Center-Aligned PWM Mode
1266
Figure 396. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
1267
Figure 397. Combined PWM Mode on Channels 1 and 3
1268
Figure 398. OCREF_CLR Input Selection Multiplexer
1269
Figure 399. Clearing Timx Tim_Ocxref
1269
Figure 400. Example of One-Pulse Mode
1270
Figure 401. Retriggerable One Pulse Mode
1272
Figure 402. Pulse Generator Circuitry
1272
Figure 403. Pulse Generation on Compare Event, for Edge-Aligned and Encoder Modes
1273
Figure 404. Extended Pulse Width in Case of Concurrent Triggers
1274
Table 279. Counting Direction Versus Encoder Signals(CC1P = CC2P = 0)
1275
Figure 405. Example of Counter Operation in Encoder Interface Mode
1276
Figure 406. Example of Encoder Interface Mode with Tim_Ti1Fp1 Polarity Inverted
1276
Figure 407. Quadrature Encoder Counting Modes
1277
Figure 408. Direction Plus Clock Encoder Mode
1278
Figure 409. Directional Clock Encoder Mode (CC1P = CC2P = 0)
1279
Figure 410. Directional Clock Encoder Mode (CC1P = CC2P = 1)
1279
Table 280. Counting Direction Versus Encoder Signals and Polarity Settings
1280
Figure 411. Index Gating Options
1281
Figure 412. Jittered Index Signals
1281
Figure 413. Index Generation for IPOS[1:0] = 11
1282
Figure 414. Counter Reading with Index Gated on Channel a (IPOS[1:0] = 11)
1282
Figure 415. Counter Reading with Index Ungated (IPOS[1:0] = 00)
1283
Figure 416. Counter Reading with Index Gated on Channel a and B
1283
Figure 417. Encoder Mode Behavior in Case of Narrow Index Pulse (IPOS[1:0] = 11)
1284
Figure 418. Counter Reset Narrow Index Pulse (Closer View, ARR = 0X07)
1285
Figure 419. Index Behavior in X1 and X2 Mode (IPOS[1:0] = 01)
1286
Figure 420. Directional Index Sensitivity
1287
Figure 421. Counter Reset as Function of FIDX Bit Setting
1287
Figure 422. Index Behavior in Clock + Direction Mode, IPOS[0] = 1
1288
Figure 423. Index Behavior in Directional Clock Mode, IPOS[0] = 1
1288
Figure 424. State Diagram for Quadrature Encoded Signals
1289
Figure 425. Up-Counting Encoder Error Detection
1290
Figure 426. Down-Counting Encode Error Detection
1291
Figure 427. Encoder Mode Change with Preload Transferred on Update (SMSPS = 0)
1292
Figure 428. Control Circuit in Reset Mode
1294
Figure 429. Control Circuit in Gated Mode
1295
Figure 430. Control Circuit in Trigger Mode
1295
Figure 431. Control Circuit in External Clock Mode 2 + Trigger Mode
1297
Figure 432. Master/Slave Timer Example
1297
Figure 433. Master/Slave Connection Example with 1 Channel Only Timers
1298
Figure 434. Gating Tim_Slv with Tim_Oc1Ref of Tim_Mstr
1299
Figure 435. Gating Tim_Slv with Enable of Tim_Mstr
1300
Figure 436. Triggering Tim_Slv with Update of Tim_Mstr
1301
Figure 437. Triggering Tim_Slv with Enable of Tim_Mstr
1301
Figure 438. Triggering Tim_Mstr and Tim_Slv with Tim_Mstr Tim_Ti1 Input
1302
Table 281. DMA Request
1303
Table 282. Effect of Low-Power Modes on TIM2/TIM3/TIM4/TIM5
1304
Table 283. Interrupt Requests
1304
Table 284. Output Control Bit for Standard Tim_Ocx Channels
1324
Table 285. TIM2/TIM3/TIM4/TIM5 Register Map and Reset Values
1341
Figure 439. TIM15 Block Diagram
1346
Figure 440. TIM16/TIM17 Block Diagram
1347
Table 286. TIM Input/Output Pins
1347
Table 287. TIM Internal Input/Output Signals
1348
Table 288. Interconnect to the Tim_Ti1 Input Multiplexer
1348
Table 289. Interconnect to the Tim_Ti2 Input Multiplexer
1349
Table 290. Timx Internal Trigger Connection
1349
Table 291. Timer Break Interconnect
1350
Table 292. System Break Interconnect
1350
Table 293. Interconnect to the Ocref_Clr Input Multiplexer
1350
Figure 441. Counter Timing Diagram with Prescaler Division Change from 1 to 2
1352
Figure 442. Counter Timing Diagram with Prescaler Division Change from 1 to 4
1352
Figure 443. Counter Timing Diagram, Internal Clock Divided by 1
1354
Figure 444. Counter Timing Diagram, Internal Clock Divided by 2
1354
Figure 445. Counter Timing Diagram, Internal Clock Divided by 4
1355
Figure 446. Counter Timing Diagram, Internal Clock Divided by N
1355
(Timx_Arr Not Preloaded)
1356
Figure 447. Counter Timing Diagram, Update Event When ARPE=0
1356
(Timx_Arr Preloaded)
1357
Figure 448. Counter Timing Diagram, Update Event When ARPE=1
1357
Figure 449. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
1358
Figure 450. Control Circuit in Normal Mode, Internal Clock Divided by 1
1359
Figure 451. Tim_Ti2 External Clock Connection Example
1359
Figure 452. Control Circuit in External Clock Mode 1
1360
Figure 453. Capture/Compare Channel (Example: Channel 1 Input Stage)
1361
Figure 454. Capture/Compare Channel 1 Main Circuit
1361
Figure 455. Output Stage of Capture/Compare Channel (Channel 1)
1362
Figure 456. Output Stage of Capture/Compare Channel (Channel 2 for TIM15)
1362
Figure 457. PWM Input Mode Timing
1365
Figure 458. Output Compare Mode, Toggle on Tim_Oc1
1367
Figure 459. Edge-Aligned PWM Waveforms (ARR=8)
1368
Figure 460. Dithering Principle
1369
Figure 461. Data Format and Register Coding in Dithering Mode
1369
Figure 462. PWM Resolution Vs Frequency
1370
Figure 463. PWM Dithering Pattern
1371
Table 294. CCR and ARR Register Change Dithering Pattern
1371
Figure 464. Combined PWM Mode on Channel 1 and 2
1373
Figure 465. Complementary Output with Symmetrical Dead-Time Insertion
1374
Figure 466. Asymmetrical Deadtime
1375
Figure 467. Dead-Time Waveforms with Delay Greater than the Negative Pulse
1375
Figure 468. Dead-Time Waveforms with Delay Greater than the Positive Pulse
1375
Figure 469. Break Circuitry Overview
1377
Figure 470. Output Behavior in Response to a Break Event on Tim_Brk
1379
Table 295. Break Protection Disarming Conditions
1380
Figure 471. Output Redirection
1381
Figure 472. Tim_Ocref_Clr Input Selection Multiplexer
1381
Figure 473. Example of One Pulse Mode
1382
Figure 474. Retriggerable One Pulse Mode
1384
Figure 475. Measuring Time Interval between Edges on 2 Signals
1384
Figure 476. Control Circuit in Reset Mode
1385
Figure 477. Control Circuit in Gated Mode
1386
Figure 478. Control Circuit in Trigger Mode
1387
Table 296. DMA Request
1389
Table 297. Effect of Low-Power Modes on TIM15/TIM16/TIM17
1390
Table 298. Interrupt Requests
1390
Feature (TIM15)
1405
Table 299. Output Control Bits for Complementary Tim_Ocx and Tim_Ocxn Channels with Break
1405
Table 300. TIM15 Register Map and Reset Values
1418
Feature (TIM16/TIM17)
1431
Table 301. Output Control Bits for Complementary Tim_Oc1 and Tim_Oc1N Channels with Break
1431
Table 302. TIM16/TIM17 Register Map and Reset Values
1444
Figure 479. Basic Timer Block Diagram
1447
Table 303. TIM Internal Input/Output Signals
1447
Figure 480. Control Circuit in Normal Mode, Internal Clock Divided by 1
1448
Figure 481. Counter Timing Diagram with Prescaler Division Change from 1 to 2
1449
Figure 482. Counter Timing Diagram with Prescaler Division Change from 1 to 4
1450
Figure 483. Counter Timing Diagram, Internal Clock Divided by 1
1451
Figure 484. Counter Timing Diagram, Internal Clock Divided by 2
1451
Figure 485. Counter Timing Diagram, Internal Clock Divided by 4
1452
Figure 486. Counter Timing Diagram, Internal Clock Divided by N
1452
Preloaded)
1453
Preloaded)
1454
Figure 489. Dithering Principle
1455
Figure 490. Data Format and Register Coding in Dithering Mode
1455
Figure 491. Fcnt Resolution Vs Frequency
1456
Figure 492. PWM Dithering Pattern
1456
Table 304. Timx_Arr Register Change Dithering Pattern
1457
Table 305. DMA Request
1457
Table 306. Effect of Low-Power Modes on TIM6/TIM7
1458
Table 307. Interrupt Request
1458
Table 308. Timx Register Map and Reset Values
1463
Figure 493. Low-Power Timer Block Diagram
1465
Table 309. STM32G4 Series LPTIM Features
1465
Table 310. LPTIM1 External Trigger Connection
1465
Table 311. LPTIM1 Input 1 Connection
1466
Table 312. LPTIM1 Input 2 Connection
1466
Figure 494. Glitch Filter Timing Diagram
1468
Table 313. Prescaler Division Ratios
1468
Figure 495. LPTIM Output Waveform, Single Counting Mode Configuration
1469
And Set-Once Mode Activated (WAVE Bit Is Set)
1470
Figure 496. LPTIM Output Waveform, Single Counting Mode Configuration
1470
Figure 497. LPTIM Output Waveform, Continuous Counting Mode Configuration
1470
Figure 498. Waveform Generation
1472
Table 314. Encoder Counting Scenarios
1475
Figure 499. Encoder Mode Counting Sequence
1476
Table 315. Effect of Low-Power Modes on the LPTIM
1476
Table 316. Interrupt Events
1477
Table 317. LPTIM Register Map and Reset Values
1487
Figure 500. IRTIM Internal Hardware Connections with TIM16 and TIM17
1488
Figure 501. AES Block Diagram
1490
Table 318. AES Internal Input/Output Signals
1490
Figure 502. ECB Encryption and Decryption Principle
1492
Figure 503. CBC Encryption and Decryption Principle
1493
Figure 504. CTR Encryption and Decryption Principle
1494
Figure 505. GCM Encryption and Authentication Principle
1495
Figure 506. GMAC Authentication Principle
1495
Figure 507. CCM Encryption and Authentication Principle
1496
Figure 508. Encryption Key Derivation for ECB/CBC Decryption (Mode 2)
1499
Figure 509. Example of Suspend Mode Management
1500
Figure 510. ECB Encryption
1501
Figure 511. ECB Decryption
1501
Figure 512. CBC Encryption
1502
Figure 513. CBC Decryption
1502
Figure 514. ECB/CBC Encryption (Mode 1)
1503
Figure 515. ECB/CBC Decryption (Mode 3)
1504
Figure 516. Message Construction in CTR Mode
1506
Figure 517. CTR Encryption
1507
Figure 518. CTR Decryption
1507
Table 319. CTR Mode Initialization Vector Definition
1507
Figure 519. Message Construction in GCM
1509
Table 320. GCM Last Block Definition
1509
Figure 520. GCM Authenticated Encryption
1510
Table 321. GCM Mode IVI Bitfield Initialization
1510
Figure 521. Message Construction in GMAC Mode
1514
Figure 522. GMAC Authentication Mode
1514
Figure 523. Message Construction in CCM Mode
1515
Figure 524. CCM Mode Authenticated Encryption
1517
Table 322. Initialization of Aes_Ivrx Registers in CCM Mode
1518
Figure 525. 128-Bit Block Construction with Respect to Data Swap
1522
Table 323. Key Endianness in Aes_Keyrx Registers (128- or 256-Bit Key Length)
1523
Figure 526. DMA Transfer of a 128-Bit Data Block During Input Phase
1524
Figure 527. DMA Transfer of a 128-Bit Data Block During Output Phase
1524
Table 324. AES Interrupt Requests
1526
Table 325. Processing Latency for ECB, CBC and CTR
1526
Table 326. Processing Latency for GCM and CCM (in Clock Cycles)
1526
Table 327. AES Register Map and Reset Values
1537
Table 328. RTC Input/Output Pins
1541
Table 329. RTC Internal Input/Output Signals
1541
Table 330. RTC Interconnection
1542
Table 331. PC13 Configuration
1542
Table 332. RTC_OUT Mapping
1544
Table 333. Effect of Low-Power Modes on RTC
1555
Table 334. RTC Pins Functionality over Modes
1555
Table 335. Interrupt Requests
1556
Table 336. RTC Register Map and Reset Values
1576
Figure 529. TAMP Block Diagram
1579
Table 337. TAMP Input/Output Pins
1580
Table 338. TAMP Internal Input/Output Signals
1580
Table 339. TAMP Interconnection
1580
Table 340. Effect of Low-Power Modes on TAMP
1583
Table 341. Interrupt Requests
1583
Table 342. TAMP Register Map and Reset Values
1592
Table 343. USART/LPUART Features
1595
Figure 530. USART Block Diagram
1596
Figure 531. Word Length Programming
1599
Figure 532. Configurable Stop Bits
1601
Figure 534. Start Bit Detection When Oversampling by 16 or 8
1605
Figure 535. Usart_Ker_Ck Clock Divider Block Diagram
1608
Figure 536. Data Sampling When Oversampling by 16
1609
Figure 537. Data Sampling When Oversampling by 8
1610
Table 344. Noise Detection from Sampled Data
1610
Table 345. Tolerance of the USART Receiver When BRR [3:0] = 0000
1613
Table 346. Tolerance of the USART Receiver When BRR[3:0] Is Different from 0000
1614
Figure 538. Mute Mode Using Idle Line Detection
1617
Figure 539. Mute Mode Using Address Mark Detection
1618
Table 347. USART Frame Formats
1619
Figure 541. Break Detection in LIN Mode Vs. Framing Error Detection
1622
(M Bits =00)
1623
Figure 542. USART Example of Synchronous Master Transmission
1623
Figure 543. USART Data Clock Timing Diagram in Synchronous Master Mode
1623
(M Bits = 01)
1624
Figure 544. USART Data Clock Timing Diagram in Synchronous Master Mode
1624
(M Bits =00)
1625
Figure 545. USART Data Clock Timing Diagram in Synchronous Slave Mode
1625
Figure 546. ISO 7816-3 Asynchronous Protocol
1627
Figure 547. Parity Error Detection Using the 1.5 Stop Bits
1629
Figure 548. Irda SIR ENDEC Block Diagram
1633
Figure 549. Irda Data Modulation (3/16) - Normal Mode
1633
Figure 550. Transmission Using DMA
1635
Figure 551. Reception Using DMA
1636
Figure 552. Hardware Flow Control between 2 Usarts
1636
Figure 553. RS232 RTS Flow Control
1637
Figure 554. RS232 CTS Flow Control
1638
FIFO Disabled)
1641
Figure 555. Wakeup Event Verified (Wakeup Event = Address Match, FIFO Disabled)
1641
Figure 556. Wakeup Event Not Verified
1641
Table 348. USART Interrupt Requests
1642
Table 349. USART Register Map and Reset Values
1679
Table 350. USART/LPUART Features
1683
Figure 557. LPUART Block Diagram
1684
Figure 558. LPUART Word Length Programming
1686
Figure 559. Configurable Stop Bits
1688
Figure 561. Lpuart_Ker_Ck Clock Divider Block Diagram
1693
Table 351. Error Calculation for Programmed Baud Rates at Lpuart_Ker_Ck_Pres= 32,768 Khz
1694
Table 352. Error Calculation for Programmed Baud Rates at Fck = 100 Mhz
1695
Table 353. Tolerance of the LPUART Receiver
1696
Figure 562. Mute Mode Using Idle Line Detection
1697
Figure 563. Mute Mode Using Address Mark Detection
1698
Figure 564. Transmission Using DMA
1700
Figure 565. Reception Using DMA
1701
Figure 566. Hardware Flow Control between 2 Lpuarts
1702
Figure 567. RS232 RTS Flow Control
1702
Figure 568. RS232 CTS Flow Control
1703
FIFO Disabled)
1706
Figure 569. Wakeup Event Verified
1706
Figure 570. Wakeup Event Not Verified
1706
Table 355. LPUART Interrupt Requests
1707
Table 356. LPUART Register Map and Reset Values
1732
Table 357. STM32G4 Series SPI and SPI/I2S Implementation
1735
Figure 571. SPI Block Diagram
1736
Figure 572. Full-Duplex Single Master/ Single Slave Application
1737
Figure 573. Half-Duplex Single Master/ Single Slave Application
1738
Figure 574. Simplex Single Master/Single Slave Application
1739
Slave in Receive-Only Mode)
1739
Figure 575. Master and Three Independent Slaves
1740
Figure 576. Multi-Master Application
1741
Figure 577. Hardware/Software Slave Select Management
1742
Figure 578. Data Clock Timing Diagram
1743
Figure 579. Data Alignment When Data Length Is Not Equal to 8-Bit or 16-Bit
1744
Figure 580. Packing Data in FIFO for Transmission and Reception
1748
Figure 581. Master Full-Duplex Communication
1751
Figure 582. Slave Full-Duplex Communication
1752
Figure 583. Master Full-Duplex Communication with CRC
1753
Figure 584. Master Full-Duplex Communication in Packed Mode
1754
Figure 585. NSSP Pulse Generation in Motorola SPI Master Mode
1757
Figure 586. TI Mode Transfer
1758
Table 358. SPI Interrupt Requests
1760
Figure 587. I2S Block Diagram
1761
Figure 588. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy)
1763
Figure 589. I 2 S Philips Standard Waveforms (24-Bit Frame)
1763
Figure 590. Transmitting 0X8Eaa33
1764
Figure 591. Receiving 0X8Eaa33
1764
Figure 592. I
1764
Figure 593. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1764
Figure 594. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length
1765
Figure 595. MSB Justified 24-Bit Frame Length
1765
Figure 596. MSB Justified 16-Bit Extended to 32-Bit Packet Frame
1766
Figure 597. LSB Justified 16-Bit or 32-Bit Full-Accuracy
1766
Figure 598. LSB Justified 24-Bit Frame Length
1766
Figure 599. Operations Required to Transmit 0X3478Ae
1767
Figure 600. Operations Required to Receive 0X3478Ae
1767
Figure 601. LSB Justified 16-Bit Extended to 32-Bit Packet Frame
1767
Figure 602. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1768
Figure 603. PCM Standard Waveforms (16-Bit)
1768
Figure 604. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
1769
Figure 605. Start Sequence in Master Mode
1770
Figure 606. Audio Sampling Frequency Definition
1771
Figure 607. I
1771
Table 359. Audio-Frequency Precision Using Standard 8 Mhz HSE
1773
Table 360. I2S Interrupt Requests
1779
Table 361. SPI/I2S Register Map and Reset Values
1791
Figure 608. SAI Functional Block Diagram
1794
Table 362. SAI Internal Input/Output Signals
1795
Table 363. SAI Input/Output Pins
1795
Figure 609. Audio Frame
1797
Figure 610. FS Role Is Start of Frame + Channel Side Identification (FSDEF = TRIS = 1)
1799
Figure 611. FS Role Is Start of Frame (FSDEF = 0)
1800
Figure 612. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr
1801
Figure 613. First Bit Offset
1801
Table 364. Mclk_X Activation Conditions
1802
Figure 614. Audio Block Clock Generator Overview
1803
Table 365. Clock Generator Programming Examples
1805
Figure 615. PDM Typical Connection and Timing
1807
Figure 616. Detailed PDM Interface Block Diagram
1808
Figure 617. Start-Up Sequence
1809
Figure 618. SAI_ADR Format in TDM, 32-Bit Slot Width
1810
Figure 619. SAI_ADR Format in TDM, 16-Bit Slot Width
1811
Figure 620. SAI_ADR Format in TDM, 8-Bit Slot Width
1812
Table 366. TDM Settings
1812
Table 367. Allowed TDM Frame Configuration
1814
Figure 621. AC'97 Audio Frame
1815
Figure 622. SPDIF Format
1816
Figure 623. Sai_Xdr Register Ordering
1817
Table 368. SOPD Pattern
1817
Table 369. Parity Bit Calculation
1817
Table 370. Audio Sampling Frequency Versus Symbol Rates
1818
Figure 624. Data Companding Hardware in an Audio Block in the SAI
1821
Figure 625. Tristate Strategy on SD Output Line on an Inactive Slot
1822
Figure 626. Tristate on Output Data Line in a Protocol Like I2S
1823
Figure 627. Overrun Detection Error
1824
Figure 628. FIFO Underrun Event
1824
Table 371. SAI Interrupt Sources
1827
Table 372. SAI Register Map and Reset Values
1857
Table 373. I2C Implementation
1860
Figure 629. I2C Block Diagram
1861
Table 374. I2C Input/Output Pins
1862
Table 375. I2C Internal Input/Output Signals
1862
Figure 630. I2C Bus Protocol
1863
Table 376. Comparison of Analog Vs. Digital Filters
1864
Figure 631. Setup and Hold Timings
1865
Figure 632. I2C Initialization Flowchart
1868
Figure 633. Data Reception
1869
Figure 634. Data Transmission
1870
Table 378. I2C Configuration
1871
Figure 635. Slave Initialization Flowchart
1873
Figure 636. Transfer Sequence Flowchart for I2C Slave Transmitter
1875
Figure 637. Transfer Sequence Flowchart for I2C Slave Transmitter
1876
Figure 638. Transfer Bus Diagrams for I2C Slave Transmitter
1877
Nostretch= 1
1877
Nostretch=0
1877
Figure 639. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
1878
Figure 640. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
1879
Figure 641. Transfer Bus Diagrams for I2C Slave Receiver
1879
Figure 642. Master Clock Generation
1881
Table 379. I2C-Smbus Specification Clock Timings
1882
Figure 643. Master Initialization Flowchart
1883
Figure 644. 10-Bit Address Read Access with HEAD10R=0
1883
Figure 645. 10-Bit Address Read Access with HEAD10R=1
1884
Figure 646. Transfer Sequence Flowchart for I2C Master Transmitter for N≤255 Bytes
1885
Figure 647. Transfer Sequence Flowchart for I2C Master Transmitter for N>255 Bytes
1886
Figure 648. Transfer Bus Diagrams for I2C Master Transmitter
1887
Figure 649. Transfer Sequence Flowchart for I2C Master Receiver for N≤255 Bytes
1889
Figure 650. Transfer Sequence Flowchart for I2C Master Receiver for N >255 Bytes
1890
Figure 651. Transfer Bus Diagrams for I2C Master Receiver
1891
Table 380. Examples of Timing Settings for Fi2Cclk = 8 Mhz
1892
Table 381. Examples of Timings Settings for Fi2Cclk = 16 Mhz
1892
Table 382. Examples of Timings Settings for Fi2Cclk = 48 Mhz
1893
Table 383. Smbus Timeout Specifications
1895
Figure 652. Timeout Intervals for T
1896
LOW:SEXT , T LOW:MEXT
1896
Table 384. Smbus with PEC Configuration
1897
Table 385. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies
1897
(Max T TIMEOUT = 25 Ms)
1898
Table 386. Examples of TIMEOUTB Settings for Various I2CCLK Frequencies
1898
Table 387. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies
1898
(Max T IDLE = 50 Μs)
1899
Figure 653. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
1900
Figure 654. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
1900
Figure 655. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
1902
Figure 656. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
1903
Figure 657. Bus Transfer Diagrams for Smbus Master Transmitter
1904
Figure 658. Bus Transfer Diagrams for Smbus Master Receiver
1906
Table 388. Effect of Low-Power Modes on the I2C
1910
Table 389. I2C Interrupt Requests
1911
Table 390. I2C Register Map and Reset Values
1927
Figure 659. Independent Watchdog Block Diagram
1929
Table 391. IWDG Register Map and Reset Values
1937
Figure 660. Watchdog Block Diagram
1939
Figure 661. Window Watchdog Timing Diagram
1940
Table 392. WWDG Register Map and Reset Values
1943
Table 393. CAN Subsystem I/O Signals
1944
Figure 662. CAN Subsystem
1945
Figure 663. FDCAN Block Diagram
1947
Figure 664. Bit Timing
1949
Table 394. DLC Coding in FDCAN
1952
Figure 665. Transceiver Delay Measurement
1954
Figure 666. Pin Control in Bus Monitoring Mode
1955
Figure 667. Pin Control in Loop Back Mode
1957
Figure 668. Message RAM Configuration
1959
Figure 669. Standard Message ID Filter Path
1961
Figure 670. Extended Message ID Filter Path
1962
Table 395. Possible Configurations for Frame Transmission
1964
Table 396. Rx FIFO Element
1967
Table 397. Rx FIFO Element Description
1967
Table 398. Tx Buffer and FIFO Element
1969
Table 399. Tx Buffer Element Description
1969
Table 400. Tx Event FIFO Element
1971
Table 401. Tx Event FIFO Element Description
1971
Table 402. Standard Message ID Filter Element
1972
Table 403. Standard Message ID Filter Element Field Description
1972
Table 404. Extended Message ID Filter Element
1973
Table 405. Extended Message ID Filter Element Field Description
1973
Table 406. FDCAN Register Map and Reset Values
2005
Table 407. STM32G4 Series USB Implementation
2009
Figure 671. USB Peripheral Block Diagram
2010
Figure 672. Packet Buffer Areas with Examples of Buffer Description Table Locations
2014
Table 408. Double-Buffering Buffer Flag Definition
2019
Table 409. Bulk Double-Buffering Memory Buffers Usage
2019
Table 410. Isochronous Memory Buffers Usage
2021
Table 411. Resume Event Detection
2023
Table 412. Reception Status Encoding
2035
Table 413. Endpoint Type Encoding
2036
Table 414. Endpoint Kind Meaning
2036
Table 415. Transmission Status Encoding
2036
Table 416. Definition of Allocated Buffer Memory
2039
Table 417. USB Register Map and Reset Values
2040
Table 418. UCPD Implementation
2043
Figure 673. UCPD Block Diagram
2044
Table 419. UCPD Signals on Pins
2044
Figure 674. Clock Division and Timing Elements
2045
Table 420. UCPD Internal Signals
2045
Table 421. 4B5B Symbol Encoding Table
2046
Figure 675. K-Code Transmission
2048
Table 422. Ordered Sets
2048
Table 423. Validation of Ordered Sets
2048
Figure 676. Transmit Order for Various Sizes of Data
2049
Table 424. Data Size
2049
Figure 677. Packet Format
2050
Figure 678. Line Format of Hard Reset
2050
Figure 679. Line Format of Cable Reset
2051
Figure 680. bist Test Data Frame
2052
Figure 681. bist Carrier Mode 2 Frame
2052
Figure 682. UCPD BMC Transmitter Architecture
2053
Figure 683. UCPD BMC Receiver Architecture
2054
Table 425. Coding for ANAMODE, ANASUBMODE and Link with Typec_Vstate_Ccx
2057
Table 426. Type-C Sequence (Source: 3A); Cable/Sink Connected (Rd on CC1; Ra on CC2)
2059
Table 427. Effect of Low Power Modes on the UCPD
2061
Table 428. UCPD Interrupt Requests
2062
Table 429. UCPD Register Map and Reset Values
2077
Debug Support
2080
Figure 685. SWJ Debug Port
2082
Table 430. SWJ Debug Port Pins
2083
Table 431. Flexible SWJ-DP Pin Assignment
2083
Figure 686. JTAG TAP Connections
2086
Table 432. JTAG Debug Port Data Registers
2088
Table 433. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
2089
Table 434. Packet Request (8-Bits)
2090
Table 435. ACK Response (3 Bits)
2091
Table 436. DATA Transfer (33 Bits)
2091
Table 437. SW-DP Registers
2092
Table 438. Cortex ® -M4 with FPU AHB-AP Registers
2093
Table 439. Core Debug Registers
2094
Table 440. Main ITM Registers
2097
Table 441. Main ETM Registers
2098
Figure 687. TPIU Block Diagram
2105
Table 442. Asynchronous TRACE Pin Assignment
2105
Table 443. Synchronous TRACE Pin Assignment
2106
Table 444. Flexible TRACE Pin Assignment
2106
Table 445. Important TPIU Registers
2110
Table 446. DBG Register Map and Reset Values
2112
Table 447. Document Revision History
2116
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ST STM32G471 Specifications
General
Brand
ST
Model
STM32G471
Category
Microcontrollers
Language
English
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