ST STM32G471 - Figure 342. Counter Reset Narrow Index Pulse (Closer View, ARR = 0 X07)

RM0440 Rev 4 1157/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
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Figure 342. Counter reset Narrow index pulse (closer view, ARR = 0x07)
The Figure 343 below shows how the index is managed in x1 and x2 modes.
MSv45772V1
Channel A
Channel B
DIR bit
Index
Counter
4 5 6 1
3
2
7
Channel A
Channel B
DIR bit
Index
Counter
5 6 7 0 1
3
2
0