ST STM32G471 User Manual

RM0440 Rev 4 413/2126
RM0440 Direct memory access controller (DMA)
423
12.5 DMA interrupts
An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.
12.6 DMA registers
Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).
Note: See Figure 31: DMA block diagram for feature implementation.
12.6.1 DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register.
Table 88. DMA interrupt requests
Interrupt request Interrupt event Event flag
Interrupt
enable bit
Channel x interrupt
Half transfer on channel x HTIFx HTIEx
Transfer complete on channel x TCIFx TCIEx
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF8 HTIF8 TCIF8 GIF8 TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5
rrrrrr r r r r rrrrrr
1514131211109876543210
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
rrrrrr r r r r rrrrrr
Bit 31 TEIF8: transfer error (TE) flag for channel 8
0: no TE event
1: a TE event occurred
Bit 30 HTIF8: half transfer (HT) flag for channel 8
0: no HT event
1: a HT event occurred
Bit 29 TCIF8: transfer complete (TC) flag for channel 8
0: no TC event
1: a TC event occurred
Bit 28 GIF8: global interrupt flag for channel 8
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English