ST STM32G471

General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440
1262/2126 RM0440 Rev 4
Note: The ARR and CCR values will be updated automatically if the DITHEN bit is set / reset (for
instance, if ARR= 0x05 with DITHEN=0, it will be updated to ARR = 0x50 with DITHEN=1).
The following sequence must be followed when resetting the DITHEN bit:
1. CEN and ARPE bits must be reset
2. The ARR[3:0] bits must be reset
3. The DITHEN bit must be reset
4. The CCIF flags must be cleared
5. The CEN bit can be set (eventually with ARPE = 1)
Figure 391. Data format and register coding in dithering mode
The minimum frequency is given by the following formula:
MSv50911V1
MSB: 16-bits, integer part
LSB: 4-bits
fractional part
326
20 6
Base compare value is
20 during 16 periods
Additional 6 cycles are spread
over the 16 periods
Register format in
dithering mode
(16-bit)
Example
b0b19
b0b19
MSB: 28-bits, integer part
LSB: 4-bits
fractional part
Register format in
dithering mode
(32-bit)
b0b31
Reserved
b31
Resolution
F
Tim
F
pwm
--------------
F
pwmMin

F
Tim
Max
Resolution
-------------------------------------
==
Dithering mode disabled: F
pwmMin
F
Tim
65536
----------------
=
Dithering mode (16-bit timer): F
pwmMin
F
Tim
65535
15
16
------
+
------------------------------
=
Dithering mode (32-bit timer): F
pwmMin
F
Tim
268435454
15
16
------
+
-------------------------------------------
=