ST STM32G471

High-resolution timer (HRTIM) RM0440
938/2126 RM0440 Rev 4
Figure 251. ADC trigger selection overview
The ADC triggers 5 to 10 are configured in the HRTIM_ADCER register, as shown on
Figure 252. The ADC triggers 5/7/9 and 6/8/10 are using the same source set.
A single source can be selected at once for these triggers (1 out of 32 possible events).
MSv47437V2
ADC
Trigger 3
OR of
multiple
sources
Master Cmp1..4 + PER
TimerC Cmp3,4 + PER
TimerD Cmp3,4 + PER
TimerE Cmp3,4 + PER
External Events 1..5
5
5
5
5
4
4
4
ADC
Trigger 1
OR of
multiple
sources
Master Cmp1..4 + PER
TimerA Cmp2,4 + PER
TimerB Cmp2,4 + PER
TimerC Cmp2,4 + PER + RST
TimerD Cmp2,4 + PER + RST
TimerE Cmp2,3,4 + RST
External Events 6..10
5
5
4
4
5
5
4
hrtim_adc
_trg1
Timer A update
Timer C update
Timer B update
Timer D update
Timer E update
Master update
AD1USRC[2:0]
AD3USRC[2:0]
AD2USRC[2:0]
AD4USRC[2:0]
Trigger 1
Update
Trigger 3
Update
TimerB Cmp3,4 + PER + RST
TimerA Cmp3,4 + PER + RST
Timer F update
TimerF Cmp3,4 + PER + RST
4
TimerF Cmp2,3,4 + PER
4
ADC
Trigger 4
OR of
multiple
sources
ADC
Trigger 2
OR of
multiple
sources
Trigger 2
Update
Trigger 4
Update
Sources in bold are available only on Trigger 1,3 or trigger 2,4
hrtim_adc
_trg3
hrtim_adc
_trg2
hrtim_adc
_trg4