ST STM32G471 User Manual

RM0440 Rev 4 2059/2126
RM0440 USB Type-C™ / USB Power Delivery interface (UCPD)
2079
USB PD transmit
On reception of a message from the protocol layer (that is, to be sent), prepare Tx message
contents by writing the UCPD_TX_ORDSET and UCPD_TX_PAYSZ registers.
The message transmission is triggered by setting the TXSEND bit, with an appropriate
value of the TXMODE bitfield.
When the data byte is transmitted, the TXIS flag is raised to request a new data write to the
UCPD_TXDR register.
Table 426. Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2)
Type-C state
ANAMODE;
ANASUBMO
DE[1:0]
CCENABL
E
PHYCCSE
L
RDCH
CC[x]
VCONN
EN
Event =>
go to
next line
Comments
Unattached.
SRC
0:Source;
11:Rp3A0
11:both
enabled
0 (don’t
care)
0:
[Norm
al]
00:
[neither]
PHYEVT
1: [VRd-
3A0]
Wait for sink attach
detect ; seen on CC1
[EVT1]
Attachwait.
SRC
0
[Rd on
CC1]
PHYEVT
2: [VRa]
Attachwait started (100-
200ms) ; now also see
the Ra => requesting
VCONN
Attached.
SRC
[VCONN =>
CC2]
0:Source;
11:Rp3A0
[SinkTxOK]
01: CC2
disable
(possible
and
recommend
ed due to
external
VCONN
switch)
10: [CC2
active]
Timer
(100 ms)
and no
PHYEVT
x
Local CC2 disconnected
from PHY (VCONN
switch connects VCONN
source to CC2
externally;
Continue to monitor
PHYEVT1
0:Source;
10:Rp1A5
[SinkTxNG]
SW
timers
(SinkTxN
G)
Source wants to initiate
message sequence
(SinkTxNG condition set
first)
0:Source;
11:Rp3A0
[SinkTxOK]
Source finished
message sequence
(SinkTxOK condition
afterwards)
PHYEVT
1:
[VOpen-
3A0]
Wait for Sink
disconnected (Vopen on
CC1)
Unattached
wait.
SRC
11:both
enabled
0 (do not
care)
1:
[discha
rge]
00:
[neither]
>0.8V
detection
(or
timer?)
Special Source
w/VCONN state (ECR
Apr 2016):
Discharge VCONN
[CC2] actively [Rdch] ; to
< 0.8V
Unattached.
SRC
0:Source;
11:Rp3A0
0:
[Norm
al]
-
[Details as first line of
table]

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English