ST STM32G471

RM0440 Rev 4 77/2126
RM0440 System and memory overview
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2 System and memory overview
2.1 System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Up to five masters:
–Cortex
®
-M4 with FPU core I-bus
–Cortex
®
-M4 with FPU core D-bus
–Cortex
®
-M4 with FPU core S-bus
–DMA1
–DMA2
• Up to nine slaves:
– Internal Flash memory on te ICode bus
– Internal Flash memory on DCode bus
– Internal SRAM1
– Internal SRAM2
– Internal CCM SRAM
– AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
– AHB2 peripherals
– Flexible static memory controller (FSMC)
– QUAD SPI memory interface (QUADSPI)
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1: