RM0440 Rev 4 899/2126
RM0440 High-resolution timer (HRTIM)
1083
Figure 227. External event counter cumulative mode (EEVxRSTM = 1, EEVxCNT = 2)
27.3.10 Delayed protection
The HRTIM features specific protection schemes, typically for resonant converters when it is
necessary to shut down the PWM outputs in a delayed manner, either once the active pulse
is completed or once a push-pull period is completed. These features are enabled with
DLYPRTEN bit in the HRTIM_OUTxR register, and are using specific external event
channels.
Delayed idle
In this mode, the active pulse is completed before the protection is activated. The selected
external event causes the output to enter in idle mode at the end of the active pulse (defined
by an output reset event in HRTIM_RSTx1R or HRTIM_RSTx2R).
Once the protection is triggered, the idle mode is permanently maintained but the counter
continues to run, until the output is re-enabled. Tx1OEN and Tx2OEN bits are not affected
by the delayed idle entry. To exit from delayed idle and resume operation, it is necessary to
overwrite Tx1OEN and Tx2OEN bits to 1. The output state changes on the first transition to
an active state following the output enable command.
Note: The delayed idle mode cannot be exited immediately after having been entered, before the
active pulse is completed: it is mandatory to make sure that the outputs are in idle state
before resuming the run mode. This can be done by waiting up to the next period, for
instance, or by polling the O1CPY and/or O2CPY status bits in the TIMxISR register.
The delayed idle mode can be applied to a single output (DLYPRT[2:0] = x00 or x01) or to
both outputs (DLYPRT[2:0] = x10).
An interrupt or a DMA request can be generated in response to a Delayed Idle mode entry.
The DLYPRT flag in HRTIM_TIMxISR is set as soon as the external event arrives,
independently from the end of the active pulse on output.
When the Delayed Idle mode is triggered, the output states can be determined using
O1STAT and O2STAT in HRTIM_TIMxISR. Both status bits are updated even if the delayed
MSv47423V2
01 2 0 1 4 02 3
EEV input
EEV edge detector
EEV counter
EEV event
PWM output
Counter
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