Analog-to-digital converters (ADC) RM0440
656/2126 RM0440 Rev 4
Figure 123. AUTODLY=1, regular continuous conversions interrupted by injected conversions
1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6
Figure 124. AUTODLY=1 in auto- injected mode (JAUTO=1)
1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2
3. Injected configuration: JAUTO=1, CHANNELS = 5,6
MS31023V3
Ignored
Injected
trigger
regular
JEOS
ADC_JDR1
ADC_JDR2
injected
regular
DLY (CH1)
DLY (CH2)
DLY (inj)
regular
ADC_DR
EOC
EOS
ADC
state
ADC_DR read access
by s/w by h/w
Indicative timings
RDY
CH1
DLY
CH5
CH2
DLY
CH6
DLY
DLY
CH1
CH3
D1
D2 D3
D6
D5
regular
injected
DLY (CH3)
ADSTART
(1)
MS31024V3
regular
JEOS
ADC_JDR1
ADC_JDR2
injected
regular
DLY (CH1)
DLY (inj)
regular
ADC_DR
EOC
EOS
ADC state
ADC_DR read access
by s/w by h/w
Indicative timings
RDY
CH1
CH6
CH2
CH5
DLY(CH2)
DLY
CH1
CH3
D1
D2 D3
D6
D5
regular
injected
No delay
ADSTART
(1)