ST STM32G471 User Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440
1304/2126 RM0440 Rev 4
29.4.26 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M4 with FPU core halted), the TIMx
counter can either continues to work normally or stops.
The behavior in debug mode can be programmed with a dedicated configuration bit per
timer in the Debug support (DBG) module.
For more details, refer to section Debug support (DBG).
29.4.27 TIM2/TIM3/TIM4/TIM5 low-power modes
29.4.28 TIM2/TIM3/TIM4/TIM5 interrupts
The TIM2/TIM3/TIM4/TIM5 can generate multiple interrupts, as shown in Table 283.
TIM_CH3 Capture/compare 3 CC3DE
TIM_CH4 Capture/compare 4 CC4DE
TIM_TRIG Trigger TDE
Table 281. DMA request (continued)
DMA acronym DMA request
Enable
control bit
Table 282. Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
Mode Description
Sleep
No effect, peripheral is active. The interrupts can cause the device to exit from Sleep
mode.
Stop
The timer operation is stopped and the register content is kept. No interrupt can be
generated.
Standby The timer is powered-down and must be reinitialized after exiting the Standby mode.
Table 283. Interrupt requests
Interrupt
acronym
Interrupt event
Event
flag
Enable
control bit
Interrupt clear
method
Exit
from
Sleep
mode
Exit from
Stop and
Standby
mode
TIM_UP Update UIF UIE write 0 in UIF Yes No
TIM_CC
Capture/compare 1 CC1IF CC1IE write 0 in CC1IF Yes No
Capture/compare 2 CC2IF CC2IE write 0 in CC2IF Yes No
Capture/compare 3 CC3IF CC3IE write 0 in CC3IF Yes No
Capture/compare 4 CC4IF CC4IE write 0 in CC4IF Yes No
TIM_TRG Trigger TIF TIE write 0 in TIF Yes No
TIM_DIR
_IDX
Index IDXF IDXIE write 0 in IDXF Yes No
Direction DIRF DIRIE write 0 in DIRF Yes No

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English