RM0440 Rev 4 135/2126
RM0440 Embedded Flash memory (FLASH) for category 3 devices
228
Bit 31 ECCD: ECC detection
DBANK=1
Set by hardware when two ECC errors have been detected (only if
ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this bit is set, a
NMI is generated.
Cleared by writing 1.
DBANK=0
Set by hardware when two ECC errors have been detected on 64-bits LSB (bits
63:0) (only if ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this
bit is set, a NMI is generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
DBANK=1
Set by hardware when one ECC error has been detected and corrected (only if
ECCC/ECCC2/ECCD/ECCD2 are previously cleared). An interrupt is generated
if ECCCIE is set.
Cleared by writing 1.
DBANK=0
Set by hardware when one ECC error as been detected and corrected on 64-bits
LSB (bits 63:0) (only if ECCC/ECCC2/ECCD/ ECCD2 are previously cleared).
Cleared by writing 1.
Bit 29 ECCD2: ECC2 detection
DBANK=0
Set by hardware when two ECC errors have been detected on 64-bits MSB
(bits127:64). This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are previously
cleared). When this bit is set, a NMI is generated.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
Bit 28 ECCC2: ECC correction
DBANK=0
Set by hardware when one ECC error has been detected and corrected on 64-
bits MSB (bits127:64). This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are
previously cleared). An interrupt is generated if ECCCIE is set.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled.
DBANK=0
This bit enables the interrupt generation when the ECCC or ECCC2 bits in the
FLASH_ECCR register are set.
DBANK=1
This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR
register is set.
Bit 23 Reserved, must be kept at reset value.
To Next Page
Loading...
Need help?
General
