ST STM32G471 User Manual

RM0440 Rev 4 1309/2126
RM0440 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
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29.5.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5)
Address offset: 0x008
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. SMSPS SMSPE Res. Res. TS[4:3] Res. Res. Res. SMS[3]
rw rw rw rw rw
1514131211109876543210
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] OCCS SMS[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 SMSPS: SMS preload source
This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to
active
0: The transfer is triggered by the Timer’s Update event
1: The transfer is triggered by the Index event
Bit 24 SMSPE: SMS preload enable
This bit selects whether the SMS[3:0] bitfield is preloaded
0: SMS[3:0] bitfield is not preloaded
1: SMS[3:0] preload is enabled
Bits 23:22 Reserved, must be kept at reset value.
Bits 19:17 Reserved, must be kept at reset value.
Bit 15 ETP: External trigger polarity
This bit selects whether tim_etr_in or tim_etr_in
is used for trigger operations
0: tim_etr_in is non-inverted, active at high level or rising edge
1: tim_etr_in is inverted, active at low level or falling edge
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf
signal.
Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
tim_trgi connected to tim_etrf (SMS=111 and TS=00111).
2: It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be
connected to tim_etrf in this case (TS bits must not be 00111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time,
the external clock input is tim_etrf.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal tim_etrp frequency must be at most 1/4 of tim_ker_ck frequency. A
prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast
external clocks on tim_etr_in.
00: Prescaler OFF
01: tim_etrp frequency divided by 2
10: tim_etrp frequency divided by 4
11: tim_etrp frequency divided by 8

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English