ST STM32G471 User Manual

RM0440 Rev 4 1561/2126
RM0440 Real-time clock (RTC)
1592
35.6.6 RTC wakeup timer register (RTC_WUTR)
This register can be written only when WUTWF is set to 1 in RTC_ICSR.
This register is write protected. The write access procedure is described in RTC register
write protection on page 1547.
Address offset: 0x14
Backup domain reset value: 0x0000 FFFF
System reset: not affected
35.6.7 RTC control register (RTC_CR)
This register is write protected. The write access procedure is described in RTC register
write protection on page 1547.
Address offset: 0x18
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
WUT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every
(WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits
of the RTC_CR register.
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE
is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2
EN
TAMP
ALRM_
TYPE
TAMP
ALRM_
PU
Res. Res.
TAMP
OE
TAMP
TS
ITSE COE OSEL[1:0] POL COSEL BKP SUB1H ADD1H
rw rw rw rw rw rw rw rw rw rw rw rw w w
1514131211109876543210
TSIE WUTIE
ALRB
IE
ALRA
IE
TSE WUTE ALRBE ALRAE Res. FMT
BYP
SHAD
REFCK
ON
TS
EDGE
WUCKSEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English