Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0440
1662/2126 RM0440 Rev 4
37.7.7 USART receiver timeout register (USART_RTOR)
Address offset: 0x14
Reset value: 0x0000 0000
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 GT[7:0]: Guard time value
This bitfield is used to program the Guard time value in terms of number of baud clock
periods.
This is used in Smartcard mode. The Transmission Complete flag is set after this guard time
value.
This bitfield can only be written when the USART is disabled (UE=0).
Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value.
Refer to Section 37.4: USART implementation on page 1595.
Bits 7:0 PSC[7:0]: Prescaler value
In IrDA low-power and normal IrDA mode:
PSC[7:0] = IrDA Normal and Low-Power baud rate
PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve
the low-power frequency: the source clock is divided by the value given in the register (8
significant bits):
In Smartcard mode:
PSC[4:0] = Prescaler value
PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide
the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to
give the division factor of the source clock frequency:
00000: Reserved - do not program this value
00001: Divides the source clock by 1 (IrDA mode)/by 2 (Smarcard mode)
00010: Divides the source clock by 2 (IrDA mode)/by 4 (Smartcard mode)
00011: Divides the source clock by 3 (IrDA mode)/by 6 (Smartcard mode)
...
11111: Divides the source clock by 15 (IrDA mode)/by 30 (Smartcard mode)
...
1111 1111: Divides the source clock by 512 (Smartcard mode)
This bitfield can only be written when the USART is disabled (UE=0).
Note: Bits [7:5] must be kept cleared if Smartcard mode is used.
This bitfield is reserved and forced by hardware to ‘0’ when the Smartcard and IrDA
modes are not supported. Refer to Section 37.4: USART implementation on page 1595.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN[7:0] RTO[23:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
RTO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw