RM0440 Rev 4 1709/2126
RM0440 Low-power universal asynchronous receiver transmitter (LPUART)
1733
38.6 LPUART registers
Refer to Section 1.2 on page 72 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32 bits).
38.6.1 LPUART control register 1 [alternate] (LPUART_CR1)
Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXF
FIE
TXFEIE
FIFO
EN
M1 Res. Res. DEAT[4:0] DEDT[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15141312111098765 43210
Res. CMIE MME M0 WAKE PCE PS PEIE
TXFN
FIE
TCIE
RXFN
EIE
IDLEIE TE RE UESM UE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 RXFFIE:RXFIFO Full interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register
Bit 30 TXFEIE:TXFIFO empty interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register
Bit 29 FIFOEN:FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
Bit 28 M1: Word length
This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = ‘00’: 1 Start bit, 8 Data bits, n Stop bit
M[1:0] = ‘01’: 1 Start bit, 9 Data bits, n Stop bit
M[1:0] = ‘10’: 1 Start bit, 7 Data bits, n Stop bit
This bit can only be written when the LPUART is disabled (UE=0).
Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate
(0x7F and 0x55 frames detection) are not supported.
Bits 27:26 Reserved, must be kept at reset value.
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