FD controller area network (FDCAN) RM0440
1948/2126 RM0440 Rev 4
Tx Handler
Controls the message transfer from the Message RAM to the CAN core. A maximum of
three Tx Buffers is available for transmission. Tx Buffer can be used as Tx FIFO or a Tx
queue. Tx Event FIFO stores Tx timestamps together with the corresponding Message ID.
Transmit cancellation is also supported.
Rx Handler
Controls the transfer of received messages from the CAN core to the external Message
RAM. The Rx Handler supports two Receive FIFOs, for storage of all messages that have
passed acceptance filtering. An Rx timestamp is stored together with each message. Up to
28 filters can be defined for 11-bit IDs, up to 8 filters for 29-bit IDs.
APB interface
Connects the FDCAN to the APB bus for configuration registers, controller configuration and
RAM access.
Message RAM interface
Connects the FDCAN access to an external 1 Kbyte Message RAM through a RAM
controller / arbiter.
44.3.1 Bit timing
The bit timing logic monitors the serial bus-line and performs sampling and adjustment of
the sample point by synchronizing on the start-bit edge and resynchronizing on the following
edges.
As shown in Figure 664, its operation may be explained simply by splitting the bit time in
three segments, as follows:
• Synchronization segment (SYNC_SEG): a bit change is expected to occur within this
time segment, having a fixed length of one time quantum (1 x tq).
• Bit segment 1 (BS1): defines the location of the sample point. It includes the
PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable
between 1 and 16 time quanta, but may be automatically lengthened to compensate for
positive phase drifts due to differences in the frequency of various nodes of the
network.
• Bit segment 2 (BS2): defines the location of the transmit point. It represents the
PHASE_SEG2 of the CAN standard, its duration is programmable between one and
eight time quanta, but may also be automatically shortened to compensate for negative
phase drifts.
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