FD controller area network (FDCAN) RM0440
1956/2126 RM0440 Rev 4
• Successful transmission
– Corresponding Tx Buffer Transmission Occurred bit TXBTO[TOx] set
– Corresponding Tx Buffer Cancellation Finished bit TXBCF[CFx] not set
• Successful transmission in spite of cancellation
– Corresponding Tx Buffer Transmission Occurred bit TXBTO[TOx] set
– Corresponding Tx Buffer Cancellation Finished bit TXBCF[CFx] set
• Arbitration loss or frame transmission disturbed
– Corresponding Tx Buffer Transmission Occurred bit TXBTO[TOx] not set
– Corresponding Tx Buffer Cancellation Finished bit TXBCF[CFx] set
In case of a successful frame transmission, and if storage of Tx events is enabled, a Tx
Event FIFO element is written with Event Type ET = 10 (transmission in spite of
cancellation).
Power down (Sleep mode)
The FDCAN can be set into power down mode controlled by clock stop request input via CC
control register CCCR[CSR]. As long as the clock stop request is active, bit CCCR[CSR] is
read as 1.
When all pending transmission requests have completed, the FDCAN waits until bus idle
state is detected. Then the FDCAN sets then CCCR[INIT] to 1 to prevent any further CAN
transfers. Now the FDCAN acknowledges that it is ready for power down by setting
CCCR[CSA] to 1. In this state, before the clocks are switched off, further register accesses
can be made. A write access to CCCR[INIT] has no effect. Now the module clock inputs
may be switched off.
To leave power down mode, the application has to turn on the module clocks before
resetting CC control register flag CCCR.CSR. The FDCAN acknowledges this by resetting
CCCR[CSA]. Afterwards, the application can restart CAN communication by resetting bit
CCCR[INIT].
Test modes
To enable write access to FDCAN test register (FDCAN_TEST), bit CCCR.TEST must be
set to 1, thus enabling the configuration of test modes and functions.
Four output functions are available for the CAN transmit pin FDCAN_TX by programming
TEST.TX. In addition to its default function (the serial data output) it can drive the CAN
Sample Point signal to monitor the FDCAN bit timing and it can drive constant dominant or
recessive values. The actual value at pin FDCAN_RX can be read from TEST.RX. Both
functions can be used to check the CAN bus physical layer.
Due to the synchronization mechanism between CAN kernel clock and APB clock domain,
there may be a delay of several APB clock periods between writing to TEST.TX until the new
configuration is visible at FDCAN_TX output pin. This applies also when reading
FDCAN_RX input pin via TEST.RX.
Note: Test modes must be used for production tests or self test only. The software control for
FDCAN_TX pin interferes with all CAN protocol functions. It is not recommended to use test
modes for application.
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