Debug support (DBG) RM0440
2104/2126 RM0440 Rev 4
Bit 20 DBG_TIM20_STOP: TIM20 counter stopped when core is halted
0: The clock of the TIM20 counter is fed even if the core is halted
1: The clock of the TIM20 counter is stopped when the core is halted
Bit19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 counter stopped when core is halted
0: The clock of the TIM17 counter is fed even if the core is halted
1: The clock of the TIM17 counter is stopped when the core is halted
Bit 17 DBG_TIM16_STOP: TIM16 counter stopped when core is halted
0: The clock of the TIM16 counter is fed even if the core is halted
1: The clock of the TIM16 counter is stopped when the core is halted
Bit 16 DBG_TIM15_STOP: TIM15 counter stopped when core is halted
0: The clock of the TIM15 counter is fed even if the core is halted
1: The clock of the TIM15 counter is stopped when the core is halted
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 DBG_TIM8_STOP: TIM8 counter stopped when core is halted
0: The clock of the TIM8 counter is fed even if the core is halted
1: The clock of the TIM8 counter is stopped when the core is halted
Bit 12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 counter stopped when core is halted
0: The clock of the TIM1 counter is fed even if the core is halted
1: The clock of the TIM1 counter is stopped when the core is halted
Bits 10:0 Reserved, must be kept at reset value.
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