RM0440 Rev 4 287/2126
RM0440 Reset and clock control (RCC)
338
Calibration of the HSI16
For TIM15 and TIM16, the primary purpose of connecting the LSE to the channel 1 input
capture is to be able to precisely measure the HSI16 system clocks (for this, the HSI16
should be used as the system clock source). The number of HSI16 clock counts between
consecutive edges of the LSE signal provides a measure of the internal clock period. Taking
advantage of the high precision of LSE crystals (typically a few tens of ppm’s), it is possible
to determine the internal clock frequency with the same resolution, and trim the source to
compensate for manufacturing, process, temperature and/or voltage related frequency
deviations.
The HSI16 oscillator has dedicated user-accessible calibration bits for this purpose.
The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio):
the precision is therefore closely related to the ratio between the two clock sources. The
higher the ratio is, the better the measurement is.
If LSE is not available, HSE/32 is the better option in order to reach the most precise
calibration possible.
Calibration of the LSI
The calibration of the LSI follows the same pattern that for the HSI16, but changing the
reference clock. It is necessary to connect LSI clock to the channel 1 input capture of the
TIM16. Then define the HSE as system clock source, the number of his clock counts
between consecutive edges of the LSI signal provides a measure of the internal low speed
clock period.
The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the
precision is therefore closely related to the ratio between the two clock sources. The higher
the ratio is, the better the measurement is.
7.2.17 Peripheral clock enable register
(RCC_AHBxENR, RCC_APBxENRy)
Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR,
RCC_APBxENRy registers.
When the peripheral clock is not active, the peripheral registers read or write accesses are
not supported.
The enable bit has a synchronization mechanism to create a glitch free clock for the
peripheral. After the enable bit is set, there is a 2 clock cycles delay before the clock be
active.
Caution: Just after enabling the clock for a peripheral, software must wait for a delay before
accessing the peripheral registers.
7.3 Low-power modes
• AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
• Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks
(Flash and SRAM1, SRAM2 and CCM SRAM interfaces) can be stopped by software
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