ST STM32G471

Reset and clock control (RCC) RM0440
320/2126 RM0440 Rev 4
Bit 14 ADC345SMEN: ADC345 clock enable
Set and cleared by software.
0: ADC345 clock disabled
1: ADC345 clock enabled
Bit 13 ADC12SMEN: ADC12 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ADC12 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: ADC12 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 12:11 Reserved, must be kept at reset value.
Bit 10 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM2 interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SRAM2 interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 9 CCMSRAMSMEN: CCM SRAM interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: CCM SRAM interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: CCM SRAM interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 GPIOGSMEN: IO port G clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port G clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port G clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 5 GPIOFSMEN: IO port F clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port F clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port F clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port E clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port E clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port D clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port D clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port C clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port C clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port B clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port B clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port A clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port A clocks enabled by the clock gating
(1)
during Sleep and Stop modes