ST STM32G471 User Manual

RM0440 Rev 4 323/2126
RM0440 Reset and clock control (RCC)
338
Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USART2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SPI3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SPI2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG
option is activated.
0: Window watchdog clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: Window watchdog clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep and Stop modes
Set and cleared by software
0: RTC APB clock disabled by the clock gating
(1)
during Sleep and Stop modes
1: RTC APB clock enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 9 Reserved, must be kept at reset value.
Bit 8 CRSSMEN: CRS timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: CRS clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: CRS clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM7 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM7 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM6 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM6 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 3 TIM5SMEN: TIM5 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM5 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM5 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 2 TIM4SMEN: TIM4 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM4 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM4 clocks enabled by the clock gating
(1)
during Sleep and Stop modes

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English