RM0440 Rev 4 663/2126
RM0440 Analog-to-digital converters (ADC)
724
conversions, with an equivalent delay equal to N x T
CONV
= N x (t
SMPL
+ t
SAR
). The flags are
set as follow:
• The end of the sampling phase (EOSMP) is set after each sampling phase
• The end of conversion (EOC) occurs once every N conversions, when the
oversampled result is available
• The end of sequence (EOS) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)
ADC operating modes supported when oversampling (single ADC mode)
In oversampling mode, most of the ADC operating modes are maintained:
• Single or continuous mode conversions
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (AUTDLY)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.
Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is
set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as
reset).
Analog watchdog
The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the
following difference:
– The RES[1:0] bits are ignored, comparison is always done on using the full 12-bit
values HT[11:0] and LT[11:0]
– the comparison is performed on the most significant 12-bit of the 16-bit
oversampled results ADC_DR[15:4]
Note: Care must be taken when using high shifting values, this will reduce the comparison range.
For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data right-
aligned, the effective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8]
must be kept reset.
Triggered mode
The averager can also be used for basic filtering purpose. Although not a very powerful filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with
TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a
user and independent from the conversion time itself.
The Figure 132 below shows how conversions are started in response to triggers during
discontinuous mode.
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