RM0440 Rev 4 691/2126
RM0440 Analog-to-digital converters (ADC)
724
21.6.3 ADC control register (ADC_CR)
Address offset: 0x08
Reset value: 0x2000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCA
L
ADCA
LDIF
DEEP
PWD
ADVREG
EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rs rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
JADST
P
ADSTP
JADST
ART
ADSTA
RT
ADDIS ADEN
rs rs rs rs rs rs
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF
to determine if this calibration applies for single-ended or differential inputs mode.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0.
The software is allowed to update the calibration factor by writing ADC_CALFACT only
when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is
ongoing)
Bit 30 ADCALDIF: Differential mode for calibration
This bit is set and cleared by software to configure the single-ended or differential inputs
mode for the calibration.
0: Writing ADCAL will launch a calibration in single-ended inputs mode.
1: Writing ADCAL will launch a calibration in differential inputs mode.
Note: The software is allowed to write this bit only when the ADC is disabled and is not
calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0
and ADEN=0).
Bit 29 DEEPPWD: Deep-power-down enable
This bit is set and cleared by software to put the ADC in Deep-power-down mode.
0: ADC not in Deep-power down
1: ADC in Deep-power-down (default reset state)
Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 28 ADVREGEN: ADC voltage regulator enable
This bits is set by software to enable the ADC voltage regulator.
Before performing any operation such as launching a calibration or enabling the ADC, the
ADC voltage regulator must first be enabled and the software must wait for the regulator
start-up time.
0: ADC Voltage regulator disabled
1: ADC Voltage regulator enabled.
For more details about the ADC voltage regulator enable and disable sequences, refer to
Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN).
The software can program this bit field only when the ADC is disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
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