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Analog-to-digital converters (ADC) RM0440

694/2126 RM0440 Rev 4

21.6.4 ADC configuration register (ADC_CFGR)

Address offset: 0x0C

Reset value: 0x8000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

JQDIS AWD1CH[4:0] JAUTO

JAWD1

AWD1

AWD1S

JQM

JDISC

DISCNUM[2:0]

DISC

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

1514131211109876543210

ALIGN

AUT

DLY

CONT

OVR

MOD

EXTEN[1:0]

EXTSE

RES[1:0] Res.

DMA

CFG

DMA

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 JQDIS: Injected Queue disable

These bits are set and cleared by software to disable the Injected Queue mechanism :

0: Injected Queue enabled

1: Injected Queue disabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which

ensures that no regular nor injected conversion is ongoing).

A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is

cleared.

Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the

analog watchdog.

00000: ADC analog input channel 0 monitored by AWD1 (available on ADC1 only)

00001: ADC analog input channel 1 monitored by AWD1

.....

10010: ADC analog input channel 18 monitored by AWD1

others: reserved, must not be used

Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to

the reset value.

The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers.

The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which

ensures that no conversion is ongoing).

Bit 25 JAUTO: Automatic injected group conversion

This bit is set and cleared by software to enable/disable automatic injected group conversion after

regular group conversion.

0: Automatic injected group conversion disabled

1: Automatic injected group conversion enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which

ensures that no regular nor injected conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit

JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the

master ADC.

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English

ST STM32G471 User Manual

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ST STM32G471 Specifications

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