RM0440 Rev 4 757/2126
RM0440 Digital-to-analog converter (DAC)
773
22.7.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
Bit 15:2 Reserved, must be kept at reset value.
Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one dac_hclk clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2 register.
This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one dac_hclk clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. DACC1DHRB[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC1DHRB[11:0]: DAC channel1 12-bit right-aligned data B
These bits are written by software. They specify 12-bit data for DAC channel1 when the
DAC operates in Double data mode.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel1.
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