RM0440 Rev 4 837/2126
RM0440 True random number generator (RNG)
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correctly (see Section 26.3.6: RNG clocking) and then it must clear the CEIS bit interrupt
flag. The CECS bit is automatically cleared when clocking condition is normal.
Note: The clock error has no impact on generated random numbers, i.e. application can still read
RNG_DR register.
CEIS is set only when CECS is set to “1” by RNG.
Noise source error detection
When a noise source (or seed) error occurs, the RNG stops generating random numbers
and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is
available in the RNG_DR register, it must not be used as it may not have enough entropy. If
the error was detected during the initialization phase the whole initialization sequence will
be automatically restarted by the RNG.
The following sequence shall be used to fully recover from a seed error after the RNG
initialization:
1. Clear the SEIS bit by writing it to “0”.
2. Read out 12 words from the RNG_DR register, and discard each of them in order to
clean the pipeline.
3. Confirm that SEIS is still cleared. Random number generation is back to normal.
26.3.8 RNG low-power usage
If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set
to “1” by setting the RNGEN bit to “0” in the RNG_CR register. As the post-processing logic
and the output buffer remain operational while RNGEN=’0’ following features are available
to software:
• If there are valid words in the output buffer four random numbers can still be read from
the RNG_DR register.
• If there are valid bits in the conditioning output internal register four additional random
numbers can be still be read from the RNG_DR register. If it is not the case the RNG
must be re-enabled by the application until at least 32 new bits have been collected
from the noise source and a complete conditioning round has been done. It
corresponds to 16 RNG clock cycles to sample new bits, and 216 AHB clock cycles to
run a conditioning round.
When disabling the RNG the user deactivates all the analog seed generators, whose power
consumption is given in the datasheet electrical characteristics section. The user also gates
all the logic clocked by the RNG clock. Note that this strategy is adding latency before a
random sample is available on the RNG_DR register, because of the RNG initialization time.
If the RNG block is disabled during initialization (i.e. well before the DRDY bit rises for the
first time), the initialization sequence resumes from where it was stopped when RNGEN bit
is set to “1”.
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