RM0440 Rev 4 905/2126
RM0440 High-resolution timer (HRTIM)
1083
The balanced idle mode has a higher priority than the burst mode: any burst mode exit
request is discarded once the balanced idle protection has been triggered. On the contrary,
if the delayed protection is exited while the burst mode is active, the burst mode is resumed
normally.
Note: Although the output state is frozen in idle mode, a number of events are still generated on
the auxiliary outputs (see Section 27.3.18) during the idle period following the delayed
protection:
- Output set/reset interrupt or DMA requests
- External event filtering based on output signal
- Capture events triggered by set/reset
Balanced idle automatic resuming
The balanced Idle mode can be configured to have an automatic resuming of operation after
a trigger.
Once the shorten pulse has been copied to the alternate output, the pulse width is reset to
its original value and the timer resumes operation: the two outputs keep on being in RUN
mode.
This is enabled by setting the BIAR bit in the HRTIM_OUTxR register.
This mode must be used only when the period in HRTIM_PERxR is greater than 6 periods
of the fHRTIM clock, that is 0xC0 if CKPSC[2:0] = 0, 0x60 if CKPSC[2:0] = 1, 0x30 if
CKPSC[2:0] = 2, ...
Note: This bit is only significant if DLYPRT[2:0] = 011 or 111, it is ignored otherwise.
Note: In balanced idle automatic resuming mode, it is mandatory to set the IDLES state to
inactive.
27.3.11 Register preload and update management
Most of HRTIM registers are buffered and can be preloaded if needed. Typically, this allows
to prevent the waveforms from being altered by a register update not synchronized with the
active events (set/reset).
When the preload mode is enabled, accessed registers are shadow registers. Their content
is transferred into the active register after an update request, either software or
synchronized with an event.
By default, PREEN bits in HRTIM_MCR and HRTIM_TIMxCR registers are reset and the
registers are not preloaded: any write directly updates the active registers. If PREEN bit is
reset while the timer is running and preload was enabled, the content of the preload
registers is directly transferred into the active registers.
Each timing unit and the master timer have their own PREEN bit. If PRREN is set, the
preload registers are enabled and transferred to the active register only upon an update
event.
There are two options to initialize the timer when the preload feature is needed:
• Enable PREEN bit at the very end of the timer initialization to have the preload
registers transferred into the active registers before the timer is enabled (by setting
MCEN and TxCEN bits).
• enable PREEN bit at any time during the initialization and force a software update
immediately before starting.
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