High-resolution timer (HRTIM) RM0440
934/2126 RM0440 Rev 4
27.3.19 Synchronizing the HRTIM with other timers or HRTIM instances
The HRTIM provides options for synchronizing multiple HRTIM instances, as a master unit
(generating a synchronization signal) or as a slave (waiting for a trigger to be synchronized).
This feature can also be used to synchronize the HRTIM with other timers, either external or
on-chip. The synchronization circuitry is controlled inside the master timer.
Synchronization output
This section explains how the HRTIM must be configured to synchronize external resources
and act as a master unit.
Four events can be selected as the source to be sent to the synchronization output. This is
done using SYNCSRC[1:0] bits in the HRTIM_MCR register, as follows:
• 00: master timer start
This event is generated when MCEN bit is set or when the timer is re-started after
having reached the period value in single-shot mode. It is also generated on a reset
which occurs during the counting (when CONT or RETRIG bits are set).
• 01: master timer compare 1 event
• 10: timer A start
This event is generated when TACEN bit is set or when the counter is reset and re-
starts counting in response to this reset. The following counter reset events are not
propagated to the synchronization output: counter roll-over in continuous mode, and
discarded reset request in single-shot non-retriggerable mode. The reset is only taken
into account when it occurs during the counting (CONT or RETRIG bits are set).
• 11: timer A compare 1 event
SYNCOUT[1:0] bits in the HRTIM_MCR register specify how the synchronization event is
generated.
The synchronization pulses are generated on the HRTIM_SCOUT output pin, with
SYNCOUT[1:0] = 1x. SYNCOUT[0] bit specifies the polarity of the synchronization signal. If
SYNCOUT[0] = 0, the HRTIM_SCOUT pin has a low idle level and issues a positive pulse of
16 f
HRTIM
clock cycles length for the synchronization). If SYNCOUT[0] = 1, the idle level is
high and a negative pulse is generated.
Note: The synchronization pulse is followed by an idle level of 16 f
HRTIM
clock cycles during which
any new synchronization request is discarded. Consequently, the maximum synchronization
frequency is f
HRTIM
/32.
The idle level on the HRTIM_SCOUT pin is applied as soon as the SYNCOUT[1:0] bits are
enabled (i.e. the bitfield value is different from 00).
The synchronization output initialization procedure must be done prior to the configuration of
the MCU outputs and counter enable, in the following order:
1. SYNCOUT[1:0] and SYNCSRC[1:0] bitfield configuration in HRTIM_MCR
2. HRTIM_SCOUT pin configuration (see the General-purpose I/Os section)
3. Master or timer A counter enable (MCEN or TACEN bit set)
When the synchronization input mode is enabled and starts the counter (using
SYNCSTRTM/SYNCSTRTx bits) simultaneously with the synchronization output mode
(SYNCSRC[1:0] = 00 or 10), the output pulse is generated only when the counter is starting
or is reset while running. Any reset request clearing the counter without causing it to start
does not affect the synchronization output.
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