High-resolution timer (HRTIM) RM0440
952/2126 RM0440 Rev 4
The HRTIM control registers can be initialized as per the power converter topology and the
timing units use case. All inputs have to be configured (source, polarity, edge-sensitivity).
The HRTIM outputs must be set up eventually, with the following sequence:
• the polarity must be defined using POLx bits in HRTIM_OUTxR
• the FAULT and IDLE states must be configured using FAULTx[1:0] and IDLESx bits in
HRTIM_OUTxR
The HRTIM outputs are ready to be connected to the MCU I/Os. In the GPIO controller, the
selected HRTIM I/Os have to be configured as per the alternate function mapping table in
the product datasheet.
From this point on, the HRTIM controls the outputs, which are in the IDLE state.
The outputs are configured in RUN mode by setting TxyOEN bits in the HRTIM_OENR
register. The 2 outputs are in the inactive state until the first valid set/reset event in RUN
mode. Any output set/reset event (except software requests using SST, SRT) are ignored as
long as TxCEN bit is reset, as well as burst mode requests (IDLEM bit value is ignored).
Similarly, any counter reset request coming from the burst mode controller is ignored (if
TxBM bit is set).
Note: When the deadtime insertion is enabled (DTEN bit set), it is necessary to force the output
state by software, using SST and RST bits, to have the outputs in a complementary state as
soon as the RUN mode is entered.
The HRTIM operation can eventually be started by setting TxCEN or MCEN bits in
HRTIM_MCR.
If the HRTIM peripheral is reset with the Reset and Clock Controller, the output control is
released to the GPIO controller and the outputs are tri stated.
27.3.25 Debug
When a microcontroller enters the debug mode (Cortex
®
-M4 with FPU core halted), the
TIMx counter either continues to work normally or stops, depending on DBG_HRTIM_STOP
configuration bit in DBG module:
• DBG_HRTIM_STOP = 0: no behavior change, the HRTIM continues to operate.
• DBG_HRTIM_STOP = 1: all HRTIM timers, including the master, are stopped. The
outputs in RUN mode enter the FAULT state if FAULTx[1:0] = 01,10,11, or keep their
current state if FAULTx[1:0] = 00. The outputs in idle state are maintained in this state.
This is permanently maintained even if the MCU exits the halt mode. This allows to
maintain a safe state during the execution stepping. The outputs can be enabled again
by settings TxyOEN bit (requires the use of the debugger).
Timer behavior during MCU halt when DBG_HRTIM_STOP = 1
The set/reset crossbar, the dead-time and push-pull unit, the idle/balanced fault detection
and all the logic driving the normal output in RUN mode are not affected by debug. The
output keeps on toggling internally, so as to retrieve regular signals of the outputs when
TxyOEN is set again (during or after the MCU halt). Associated triggers and filters are also
following internal waveforms when the outputs are disabled.
FAULT inputs and events (any source) are enabled during the MCU halt.
Fault status bits can be set and TxyOEN bits reset during the MCU halt if a fault occurs at
that time (TxyOEN and TxyODS are not affected by DBG_HRTIM_STOP bit state).
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