RM0440 Rev 4 971/2126
RM0440 High-resolution timer (HRTIM)
1083
Bits 31:28 UPDGAT[3:0]: Update gating
These bits define how the update occurs relatively to the burst DMA transaction and the external
update request on update enable inputs hrtim_upd_en[3:1] (see Table 209).
The update events, as mentioned below, can be: MSTU, TFU, TEU, TDU, TCU, TBU, TAU, TxRSTU,
TxREPU.
0000: The update occurs independently from the DMA burst transfer
0001: The update occurs when the DMA burst transfer is completed
0010: The update occurs on the update event following the DMA burst transfer completion
0011: The update occurs on a rising edge on hrtim_upd_en1
0100: The update occurs on a rising edge on hrtim_upd_en2
0101: The update occurs on a rising edge on hrtim_upd_en3
0110: The update occurs on the update event following a rising edge on hrtim_upd_en1
0111: The update occurs on the update event following a rising edge on hrtim_upd_en2
1000: The update occurs on the update event following a rising edge on hrtim_upd_en3
Others: Reserved
Note: This bitfield must be reset before programming a new value.
For UPDGAT[3:0] values equal to 0001, 0011, 0100, 0101, it is possible to have multiple
concurrent update source (for instance RSTU and DMA burst).
Bit 27 PREEN: Preload enable
This bit enables the registers preload mechanism and defines whether a write access into a preload-
able register is done into the active or the preload register.
0: Preload disabled: the write access is directly done into the active register
1: Preload enabled: the write access is done into the preload register
Bits 26:25 DACSYNC[1:0] DAC synchronization
A DAC synchronization event is generated when the timer update occurs. These bits are defining on
which output the DAC synchronization is sent (refer to Section 27.3.21: DAC triggers for connections
details).
00: No DAC trigger generated
01: Trigger generated on hrtim_dac_trg1
10: Trigger generated on hrtim_dac_trg2
11: Trigger generated on hrtim_dac_trg3
Bit 24 MSTU: Master timer update
Register update is triggered by the master timer update.
0: Update by master timer disabled
1: Update by master timer enabled
Bit 23 TEU: Timer E update
Register update is triggered by the timer E update
0: Update by timer E disabled
1: Update by timer E enabled
Note: This bit is reserved for HRTIM_TIMECR. It is only available for HRTIM_TIMACR,
HRTIM_TIMBCR, HRTIM_TIMCCR, HRTIM_TIMDCR, HRTIM_TIMFCR.
Bit 22 TDU: Timer D update
Register update is triggered by the timer D update
0: Update by timer D disabled
1: Update by timer D enabled
Note: This bit is reserved for HRTIM_TIMDCR. It is only available for HRTIM_TIMACR,
HRTIM_TIMBCR, HRTIM_TIMCCR, HRTIM_TIMECR, HRTIM_TIMFCR.
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