RM0440 Rev 4 973/2126
RM0440 High-resolution timer (HRTIM)
1083
Bits 13:12 DELCMP2[1:0]: CMP2 auto-delayed mode
This bitfield defines whether the compare register is behaving in standard mode (compare match
issued as soon as counter equal compare), or in auto-delayed mode (see Section : Auto-delayed
mode).
00: CMP2 register is always active (standard compare mode)
01: CMP2 value is recomputed and is active following a capture 1 event
10: CMP2 value is recomputed and is active following a capture 1 event, or is recomputed and
active after compare 1 match (timeout function if capture event is missing)
11: CMP2 value is recomputed and is active following a capture 1 event, or is recomputed and
active after compare 3 match (timeout function if capture event is missing)
Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set).
Bit 11 SYNCSTRTx: Synchronization starts timer x
This bit defines the timer x behavior following the synchronization event:
0: No effect on timer x
1: A synchronization input event starts the timer x
Bit 10 SYNCRSTx: Synchronization resets timer x
This bit defines the timer x behavior following the synchronization event:
0: No effect on timer x
1: A synchronization input event resets the timer x
Bit 9 RSYNCU: Re-synchronized update
This bit specifies whether update source coming outside from the timing unit must be synchronized:
0: The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is
set) or from a software update (TxSWU bit) is taken into account immediately
1: The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is
set) or from a software update (TxSWU bit) is taken into account on the following reset/roll-over
event.
Note: This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise.
Bits 8:7 INTLVD[1:0]: Interleaved mode
This bitfield is significant only when the HALF bit is reset. It enables the interleaved mode.
00: Interleaved mode disabled
01: Triple interleaved mode: when HRTIM_PERxR register is written, the HRTIM_CMP1xR active
register is automatically updated with HRTIM_PERxR/3 value, and the HRTIM_CMP2xR active
register is automatically updated with 2x (HRTIM_PERxR/3) value.
10: Quad interleaved mode: when HRTIM_PERxR register is written, the HRTIM_CMP1xR active
register is automatically updated with HRTIM_PERxR/4 value, the HRTIM_CMP2xR active
register is automatically updated with HRTIM_PERxR/2 value and
the HRTIM_CMP3xR active
register is automatically updated with 3x (HRTIM_PERxR/4) value.
11: Interleaved mode disabled
Bit 6 PSHPLL: Push-pull mode enable
This bit enables the push-pull mode.
0: Push-pull mode disabled
1: Push-pull mode enabled
Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set).
Bit 5 HALF: Half mode enable
This bit enables the half duty-cycle mode: the HRTIM_CMP1xR active register is automatically
updated with HRTIM_PERxR/2 value when HRTIM_PERxR register is written.
0: Half mode disabled
1: Half mode enabled
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