RM0440 Rev 4 991/2126
RM0440 High-resolution timer (HRTIM)
1083
27.5.25 HRTIM timer x capture 2 register (HRTIM_CPT2xR)
(x = A to F)
Address offset: Block A: 0x0B4
Address offset: Block B: 0x134
Address offset: Block C: 0x1B4
Address offset: Block D: 0x234
Address offset: Block E: 0x2B4
Address offset: Block F: 0x334
Reset value: 0x0000 0000
Note: In up/down mode (UDM bit set to 1), the capture value is referred to:
- counting reset, when up-counting
- the PER event when down counting
The DIR bit allows to discriminate the up-down phases when reading the captured value.
Note: This is a regular resolution register: for HR clock prescaling ratio below 32
(CKPSC[2:0] < 5), the least significant bits of the counter are not significant. They cannot be
written and return 0 when read.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DIR
r
1514131211109876543210
CPT2x[15:0]
rrrrrrrrrrrrrrrr
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 DIR: Timer x capture 1 direction status
This register holds the counting direction value when the capture 1 event occurred:
0: timer is up-counting
1: timer is down-counting
In up-counting mode (UDM bit reset), the DIR bit is always read as 0.
Bits 15:0 CPT2x[15:0]: Timer x capture 2 value
This register holds the counter value when the capture 2 event occurred.
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