High-resolution timer (HRTIM) RM0440
994/2126 RM0440 Rev 4
27.5.27 HRTIM timer x output 1 set register (HRTIM_SETx1R) (x = A to F)
Address offset: Block A: 0x0BC
Address offset: Block B: 0x13C
Address offset: Block C: 0x1BC
Address offset: Block D: 0x23C
Address offset: Block E: 0x2BC
Address offset: Block F: 0x33C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDAT
E
EXT
EVNT1
0
EXT
EVNT9
EXT
EVNT8
EXT
EVNT7
EXT
EVNT6
EXT
EVNT5
EXT
EVNT4
EXT
EVNT3
EXT
EVNT2
EXT
EVNT1
TIM
EVNT9
TIM
EVNT8
TIM
EVNT7
TIM
EVNT6
TIM
EVNT5
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
TIM
EVNT4
TIM
EVNT3
TIM
EVNT2
TIM
EVNT1
MST
CMP4
MST
CMP3
MST
CMP2
MST
CMP1
MST
PER
CMP4 CMP3 CMP2 CMP1 PER
RESYN
C
SST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 UPDATE: Registers update (transfer preload to active)
Register update event forces the output to its active state.
Bit 30 EXTEVNT10: External event 10
Refer to EXTEVNT1 description.
Bit 29 EXTEVNT9: External event 9
Refer to EXTEVNT1 description.
Bit 28 EXTEVNT8: External event 8
Refer to EXTEVNT1 description.
Bit 27 EXTEVNT7: External event 7
Refer to EXTEVNT1 description.
Bit 26 EXTEVNT6: External event 6
Refer to EXTEVNT1 description.
Bit 25 EXTEVNT5: External event 5
Refer to EXTEVNT1 description.
Bit 24 EXTEVNT4: External event 4
Refer to EXTEVNT1 description.
Bit 23 EXTEVNT3: External event 3
Refer to EXTEVNT1 description.
Bit 22 EXTEVNT2: External event 2
Refer to EXTEVNT1 description.
Bit 21 EXTEVNT1: External event 1
External event 1 forces the output to its active state.
Bit 20 TIMEVNT9: Timer event 9
Refer to TIMEVNT1 description.
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