Configuring the Internal Baseband Source
R&S
®
SMBV100B
92User Manual 1178.4460.02 ─ 03
Table 3-2: Output connectors for the reference clock signal
Connector Location GUI selection
User x Front and rear panel
To configure the connector:
●
"Custom. Dig. Mod/Digital Standard > Clock
Settings > Global Connectors > Direction >
Output"
●
"Custom. Dig. Mod/Digital Standard > Clock
Settings > Global Connectors > Signal >
Symbol Clock"
To enable the clock source
●
"Custom. Dig. Mod/Digital Standard > Clock
Settings > Clock Source > Internal"
Synchronizing data signals and clock signals
The synchronization is always based on the positive edge of the clock.
Related settings:
●
Chapter 3.4.2.3, "Clock Settings", on page 115
●
Chapter 10.2, "Configuring the Global Connectors", on page 515
●
Clock settings in the dialogs of the firmware options
Control Signals
The following control signals are processed in the R&S SMBV100B:
●
"Burst Gate" for power ramping
●
"Level Attenuation" for power ramping
●
"CW/Mod" for controlling the CW (continuous wave) mode
A dedicated internal "Control Data Editor" is provided for defining the control signals.
Refer to Chapter 3.5.3.8, "Control and Marker Lists Editor", on page 130 for a descrip-
tion on the provided settings.
Continuous Wave Mode
The "CW" signal turns off digital modulation. The signal is output in unmodulated form.
The CW/Mod control signal is generated internally and is output at one of the User x
connectors.
Power Ramping and Level Attenuation
The R&S SMBV100B uses the two control signals "Burst Gate" and "Lev_Att" to trigger
the power ramping and level attenuation functions.
The instrument internally generates control signals as configured in Chapter 3.5.3.8,
"Control and Marker Lists Editor", on page 130; the signals can be output on the User
x connectors.
●
Burst gate control signal
The "Burst Gate" signal is a rectangular pulse signal with variable low and high
periods. Signal generation is restricted to the gate high periods. If the power ramp-
ing function is enabled, each transition between two gate periods of the "Burst
Gate" signal triggers the generation of a ramp. Further settings define the form and
Common Functions and Settings in the Baseband Domain
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