High-resolution timer (HRTIM) RM0440
1028/2126 RM0440 Rev 4
Bits 15:14 FEROM[1:0]: Fault and event roll-over mode
This bit defines when the roll-over is generated, in up-down counting mode. It only concerns the Roll-
over event used by the fault and event counters.
00: Event generated when the counter is equal to 0 or to HRTIM_PERxR value
01: Event generated when the counter is equal to 0
10: Event generated when the counter is equal to HRTIM_PERxR
11: Reserved
Note: This setting only applies when the UDM bit is set. It is not significant otherwise.
Note: This bitfield cannot be changed once the timer is operating (TxEN bit set).
Bits 13:12 BMROM[1:0]: Burst mode roll-over mode
This bit defines when the roll-over is generated, in up-down counting mode. It only concerns the roll-
over event used in the burst mode controller, as clock as burst mode trigger.
00: Event generated when the counter is equal to 0 or to HRTIM_PERxR value
01: Event generated when the counter is equal to 0
10: Event generated when the counter is equal to HRTIM_PERxR
11: Reserved
Note: This setting only applies when the UDM bit is set. It is not significant otherwise.
Note: This parameter cannot be changed once the timer is operating (TxEN bit set).
Bits 11:10 ADROM[1:0]: ADC roll-over mode
This bit defines when the roll-over is generated, in up-down counting mode. It only concerns the roll-
over event which triggers the ADC.
00: Event generated when the counter is equal to 0 or to HRTIM_PERxR value
01: Event generated when the counter is equal to 0
10: Event generated when the counter is equal to HRTIM_PERxR
11: Reserved
Note: This setting only applies when the UDM bit is set. It is not significant otherwise.
Note: This bitfield cannot be changed once the timer is operating (TxEN bit set).
Bits 9:8 OUTROM[1:0]: Output roll-over mode
This bit defines when the roll-over is generated, in up-down counting mode. It only concerns the roll-
over event which sets and/or resets the ouputs, as per HRTIM_SETxyR and HRTIM_RSTxyR
settings.
00: Event generated when the counter is equal to 0 or to HRTIM_PERxR value
01: Event generated when the counter is equal to 0
10: Event generated when the counter is equal to HRTIM_PERxR
11: Reserved
Note: This setting only applies when the UDM bit is set. It is not significant otherwise.
Note: This bitfield cannot be changed once the timer is operating (TxEN bit set).
Bits 7:6 ROM[1:0]: Roll-over mode
This bit defines when the roll-over is generated, in up-down counting mode. It only concerns the roll-
over event with the following destinations: update trigger (to transfer content from preload to active
registers), IRQ and DMA requests, repetition counter decrement and external event filtering.
00: Event generated when the counter is equal to 0 or to HRTIM_PERxR value
01: Event generated when the counter is equal to 0
10: Event generated when the counter is equal to HRTIM_PERxR
11: Reserved
Note: This setting only applies when the UDM bit is set. It is not significant otherwise.
Note: This bitfield cannot be changed once the timer is operating (TxEN bit set).
Bit 5 Reserved, must be kept at reset value.
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