RM0440 Rev 4 1027/2126
RM0440 High-resolution timer (HRTIM)
1083
27.5.49 HRTIM timer x control register 2 (HRTIM_TIMxCR2) (x = A to F)
Address offset: Block A: 0x0EC
Address offset: Block B: 0x16C
Address offset: Block C: 0x1EC
Address offset: Block D: 0x26C
Address offset: Block E: 0x2EC
Address offset: Block F: 0x36C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TRG
HLF
Res. Res.
GT
CMP3
GT
CMP1
rw rw rw
1514131211109876543210
FEROM[1:0] BMROM[1:0] ADROM[1:0] OUTROM[1:0] ROM[1:0] Res. UDM Res. DCDR DCDS DCDE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bit 20 TRGHLF: Triggered-half mode
This bitfield defines whether the compare 2 register is behaving in standard mode (compare match
issued as soon as counter equal compare), or in triggered-half mode (see Section : Triggered-half
mode).
0: CMP2 register is written by the user only (standard compare mode)
1: CMP2 value is set by hardware as soon as a capture 1 event occurs. It is loaded with the
(capture 1 divided by 2) value. The initial value can be written by the user (as long as TRGHLF is
reset), but is ignored once the first capture has been triggered (the preload mechanism is
disabled for CMP2 when the TRGHLF bit is set).
Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set).
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 GTCMP3: Greater than compare 3 PWM mode
This bit defines the compare 3 operating mode.
0: The compare 3 event is generated when the counter is equal to the compare value (compare
match mode)
1: The compare 3 event is generated when the counter is greater than the compare value. If the
compare value is changed on-the-fly, the new compare value is compared with the current counter
value and an output SET or RESET can be generated.
Bit 16 GTCMP1: Greater than compare 1 PWM mode
This bit defines the compare 1 operating mode.
0: The compare 1 event is generated when the counter is equal to the compare value (compare
match mode)
1: The compare 1 event is generated when the counter is greater than the compare value. If the
compare value is changed on-the-fly, the new compare value is compared with the current counter
value and an output SET or RESET can be generated.
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