Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1134/2126 RM0440 Rev 4
their active level together. Note that because of the resynchronization on MOE,
the dead-time duration is slightly longer than usual (around 2 tim_ker_ck clock
cycles).
– If OSSI=0, the timer releases the output control (taken over by the GPIO controller
which forces a Hi-Z state), otherwise the enable outputs remain or become high as
soon as one of the CCxE or CCxNE bits is high.
• The break status flag (SBIF, BIF and B2IF bits in the TIMx_SR register) is set. An
interrupt is generated if the BIE bit in the TIMx_DIER register is set. A DMA request
can be sent if the BDE bit in the TIMx_DIER register is set.
• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event (UEV). As an example, this can be used to perform a
regulation. Otherwise, MOE remains low until the application sets it to ‘1’ again. In this
case, it can be used for security and the break input can be connected to an alarm from
power drivers, thermal sensors or any security components.
Note: The break inputs are active on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF and B2IF
cannot be cleared.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows to freeze the
configuration of several parameters (dead-time duration, tim_ocx/tim_ocxn polarities and
state when disabled, OCxM configurations, break enable and polarity). The application can
choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register.
Refer to Section 28.6.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8, 20).
The LOCK bits can be written only once after an MCU reset.
Figure 317 shows an example of behavior of the outputs in response to a break.
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