Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1188/2126 RM0440 Rev 4
28.6.6 TIMx event generation register (TIMx_EGR)(x = 1, 8, 20)
Address offset: 0x014
Reset value: 0x0000
Bit 2 CC2IF: Capture/compare 2 interrupt flag
Refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output: This flag is set by hardware when the counter
matches the compare value, with some exception in center-aligned mode (refer to the CMS
bits in the TIMx_CR1 register description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input: This bit is set by hardware on a capture. It is
cleared by software or by reading the TIMx_CCR1 register.
0: No input capture occurred
1:The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on tim_ic1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow or underflow regarding the repetition counter value (update if repetition counter
= 0) and if the UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by a trigger event (refer to Section 28.6.3: TIMx slave mode
control register (TIMx_SMCR)(x = 1, 8, 20)), if URS=0 and UDIS=0 in the TIMx_CR1
register.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. B2G BG TG COMG CC4G CC3G CC2G CC1G UG
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Bits 15:9 Reserved, must be kept at reset value.
Bit 8 B2G: Break 2 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0:No action
1:A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt
can occur if enabled.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0:No action
1:A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
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