RM0440 Rev 4 1217/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
1226
28.6.27 TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8, 20)
Address offset: 0x060
Reset value: 0x0000 0001
Bits 11:8 TI2SEL[3:0]: Selects tim_ti2[0..15] input
0000: tim_ti2_in0: TIMx_CH2
0001: tim_ti2_in1
...
1111: tim_ti2_in15
Refer to Section 28.3.2: TIM1/TIM8/TIM20 pins and internal signals for interconnects list.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: Selects tim_ti1[0..15] input
0000: tim_ti1_in0: TIMx_CH1
0001: tim_ti1_in1
...
1111: tim_ti1_in15
Refer to Section 28.3.2: TIM1/TIM8/TIM20 pins and internal signals for interconnects list.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2]
rw rw
1514131211109876543210
ETRSEL[1:0]
BK
CMP4P
BK
CMP3P
BK
CMP2P
BK
CMP1P
BKINP
BK
CMP8E
BK
CMP7E
BK
CMP6E
BK
CMP5E
BK
CMP4E
BK
CMP3E
BK
CMP2E
BK
CMP1E
BKINE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: etr_in source selection
These bits select the etr_in input source.
0000: tim_etr0: TIMx_ETR input
0001: tim_etr1
...
1111: tim_etr15
Refer to Section 28.3.2: TIM1/TIM8/TIM20 pins and internal signals for product specific
implementation.
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 13 BKCMP4P: tim_brk_cmp4 input polarity
This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the
BKP polarity bit.
0: tim_brk_cmp4 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
1: tim_brk_cmp4 input polarity is inverted (active high if BKP=0, active low if BKP=1)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
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