General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440
1330/2126 RM0440 Rev 4
29.5.20 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2, 5)
Address offset: 0x038
Reset value: 0x0000 0000
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 CCR2[19:0]: Capture/compare 1 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is
loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on tim_oc2 output.
Non-dithering mode (DITHEN = 0)
The register holds the compare value in CCR2[15:0]. The CCR2[19:16] bits are reset.
Dithering mode (DITHEN = 1)
The register holds the integer part in CCR2[19:4]. The CCR2[3:0] bitfield contains the
dithered part.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (tim_ic2). The
TIMx_CCR2 register is read-only and cannot be programmed.
Non-dithering mode (DITHEN = 0)
The CCR2[15:0] bits hold the capture value. The CCR2[19:16] bits are reserved.
Dithering mode (DITHEN = 1)
The register holds the capture in CCR2[19:0]. The CCR2[3:0] bits are reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
CCR2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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