General-purpose timers (TIM15/TIM16/TIM17) RM0440
1416/2126 RM0440 Rev 4
30.7.20 TIM15 alternate function register 2 (TIM15_AF2)
Address offset: 0x064
Reset value: 0x0000 0000
Bit 2 BKCMP2E: tim_brk_cmp2 enable
This bit enables the tim_brk_cmp2 for the timer’s tim_brk input. tim_brk_cmp2 output is
‘ORed’ with the other tim_brk sources.
0: tim_brk_cmp2 input disabled
1: tim_brk_cmp2 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIM15_BDTR register).
Bit 1 BKCMP1E: tim_brk_cmp1 enable
This bit enables the tim_brk_cmp1 for the timer’s tim_brk input. tim_brk_cmp1 output is
‘ORed’ with the other tim_brk sources.
0: tim_brk_cmp1 input disabled
1: tim_brk_cmp1 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIM15_BDTR register).
Bit 0 BKINE: TIMx_BKIN input enable
This bit enables the TIMx_BKIN alternate function input for the timer’s tim_brk input.
TIMx_BKIN input is ‘ORed’ with the other tim_brk sources.
0: TIMx_BKIN input disabled
1: TIMx_BKIN input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIM15_BDTR register).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OCRSEL[2:0]
rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:16 OCRSEL[2:0]: ocref_clr source selection
These bits select the ocref_clr input source.
000: tim_ocref_clr0
001: tim_ocref_clr1
010: tim_ocref_clr2
011: tim_ocref_clr3
100: tim_ocref_clr4
101: tim_ocref_clr5
110: tim_ocref_clr6
111: tim_ocref_clr7
Refer to Section 30.4.2: TIM15/TIM16/TIM17 pins and internal signals for product specific
implementation.
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIM15_BDTR register).
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